1
James C Allen, Wendy B Bartlett, Hoke S Johnson III, Steven D Fisher, Richard O Larson, John C Peck: Multiprocessor multisystem communications network. Tandem Computers Incorporated, Townsend & Townsend, May 19, 1987: US04667287 (155 worldwide citation)

A plurality of multiprocessor systems is arranged in a high speed network to allow any processor in one system to communicate with any processor in another system. The network is configured as a multi-node dual bidirectional ring having a multiprocessor system at each node. Packets of information ma ...


2
Chris W Eidler, Hoke S Johnson III, Kaushik S Shah: Method and apparatus for transferring data through a staging memory. Micro Technology, Mark D Rowland, Joseph M Guiliano, May 24, 1994: US05315708 (66 worldwide citation)

A method and apparatus for transferring data from one device interface to another device interface via elements of a staging memory and a direct memory access (DMA) channel.


3
David H Jaffe, Hoke S Johnson III, Chris W Eidler: Method and apparatus for scheduling access to a CSMA communication medium of a node having arbitration circuit. MTI Technology Corporation, Mark D Rowland, Joseph M Guiliano, October 25, 1994: US05359320 (47 worldwide citation)

A scheduling mechanism is provided for controlling when the arbitration circuit of a node sharing a CSMA communication medium is to start CSMA arbitration for access to the communication medium once the node has a message ready for transmission, the scheduling mechanism delaying the arbitration circ ...


4
David T Powers, David H Jaffe, Larry P Henson, Hoke S Johnson III, Joseph S Glider, Thomas E Idleman: Apparatus and method for controlling data flow between a computer and memory devices. Micro Technology, Townsend and Townsend Khourie and Crew, May 18, 1993: US05212785 (38 worldwide citation)

A method and apparatus for controlling data flow between a computer and a group of memory devices arranged in a particular logical configuration. The system includes a group of first level controllers and a group of second level controllers. The first level controllers and the second level controlle ...


5
David H Jaffe, Hoke S Johnson III, Chris W Eidler: Method and apparatus for scheduling access to a CSMA communication medium. MTI Technology Corporation, Townsend and Townsend and Crew, January 16, 1996: US05485147 (37 worldwide citation)

A scheduling mechanism is provided for controlling when the arbitration circuit of a node sharing a CSMA communication medium is to start CSMA arbitration for access to the communication medium once the node has a message ready for transmission, the scheduling mechanism delaying the arbitration circ ...


6
David H Jaffe, Hoke S Johnson III, Chris W Eidler: Method and apparatus for scheduling access to a CSMA communication medium. Micro Technology, Mark D Rowland, December 29, 1992: US05175537 (26 worldwide citation)

A scheduling mechanism is provided for controlling when the arbitration circuit of a node sharing a CSMA communication medium is to start CSMA arbitration for access to the communication medium once the node has a message ready for transmission, the scheduling mechanism delaying the arbitration circ ...


7
Kaushik S Shah, Joseph S Glider, Edward E Asato, Hoke S Johnson III, Duc H Trang: Dual channel data block transfer bus. MIT Technology, Townsend and Townsend Khourie and Crew, October 24, 1995: US05461723 (24 worldwide citation)

A block transfer data bus having two separate paths, with each element coupled to the bus having the ability to arbitrate for use of one or the other or both of the bus halves. Each bus half includes an address/data bus portion for sending/receiving the data and addresses. A separate control bus por ...


8
Hoke S Johnson III: Method and circuit for decoding a Manchester code signal. SF2 Corporation, Mark D Rowland, June 11, 1991: US05023891 (19 worldwide citation)

A circuit for decoding a high speed Manchester encoded digital communication signal is provided. The circuit includes a pair of latch circuits which are used to detect clock edges in the encoded signal for providing respectively set and reset pulses to a third latch circuit, an output of which compr ...


9
David T Powers, David H Jaffe, Larry P Henson, Hoke S Johnson III, Joseph S Glider, Thomas E Idleman: Apparatus and method for controlling data flow between a computer and memory devices. Micro Technology, Townsend and Townsend and Crew, July 22, 1997: US05651110 (8 worldwide citation)

A method and apparatus for controlling data flow between a computer and a group of memory devices arranged in a particular logical configuration. The system includes a group of first level controllers and a group of second level controllers. The first level controllers and the second level controlle ...


10
David H Jaffe, Hoke S Johnson III, Chris W Eidler: Method and apparatus for scheduling access to a CSMA communication medium. MTI Technology Corporation, Mark D Rowland, Joseph M Guiliano, November 1, 1994: US05361063 (7 worldwide citation)

A scheduling mechanism is provided for controlling when the arbitration circuit of a node sharing a CSMA communication medium is to start CSMA arbitration for access to the communication medium once the node has a message ready for transmission, the scheduling mechanism delaying the arbitration circ ...