1
Sau Ching Wong, Hock Chuen So, Stanley J Kopec Jr, Robert F Hartmann: Programmable logic device with array blocks connected via programmable interconnect. Altera Corporation, Robert R Jackson, October 3, 1989: US04871930 (308 worldwide citation)

A programmable logic device having a relatively small number of programmable product terms ("P-terms") feeding each fixed combinatorial logic device, and additional "expander" programmable P-terms which do not directly feed a fixed device. Relatively simple logic functions can be performed by suitab ...


2
Sau Ching Wong, Hock Chuen So, Stanley J Kopec Jr, Robert F Hartmann: Programmable logic device with array blocks with programmable clocking. Altera Corporation, Robert R Jackson, March 27, 1990: US04912342 (221 worldwide citation)

A programmable logic device having a relatively small number of programmable product terms ("P-terms") feeding each fixed combinatorial logic device, and additional "expander" programmable P-terms which do not directly feed a fixed device. Relatively simple logic functions can be performed by suitab ...


3
Sau Ching Wong, Hock Chuen So: Data management for multi-bit-per-cell memories. Multi Level Memory Technology, David T Millers, March 11, 2003: US06532556 (218 worldwide citation)

A multi-bit-per-cell memory reduces the effect of defects and data errors by scrambling data bits before writing data. The scrambling prevents storage of consecutive bits in the same memory cell. When a memory cell is defective or produces an error, the bits read from the memory cell do not create c ...


4
Hock Chuen So, Sau Ching Wong: Programmable logic devices with spare circuits for use in replacing defective circuits. Altera Corporation, Robert R Jackson, February 6, 1990: US04899067 (204 worldwide citation)

A programmable logic device having a plurality of word lines and a plurality of bit lines, each of which is programmably interconnectable to at least one of the word lines for producing on each bit line a signal which is a logical function of the signal or signals on the word line or lines to which ...


5
Bruce B Pedersen, David Chiang, Francis B Heile, Cameron McClintock, Hock Chuen So, James A Watson: High-density erasable programmable logic device architecture using multiplexer interconnections. Altera Corporation, Jeffrey H Ingerman, August 31, 1993: US05241224 (135 worldwide citation)

A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to logic array blocks. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes the user's ability to route a selected line t ...


6
Kevin A Norman, Hock Chuen So, Kerry S Veenstra, Sau Ching Wong: Multifunction flip-flop-type circuit. Altera Corporation, Robert R Jackson, September 5, 1989: US04864161 (59 worldwide citation)

A flip-flop-type circuit capable of operating either as a conventional D flip-flop or as a device which merely passes through the data applied to it (so-called "flow-through mode"). In the flow-through mode, the circuit has the additional capability of being able to latch in the data flowing through ...


7
Bruce B Pedersen, David Chiang, Francis B Heile, Cameron McClintock, Hock Chuen So, James A Watson: High-density erasable programmable logic device architecture using multiplexer interconnections. Altera Corporation, Jeffrey H Ingerman, Robert W Morris, December 7, 1993: US05268598 (26 worldwide citation)

A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to logic array blocks. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes the user's ability to route a selected line t ...


8
Bruce B Pedersen, David Chiang, Francis B Heile, Cameron McClintock, Hock Chuen So, James A Watson: High-density erasable programmable logic device architecture using multiplexer interconnections. Altera Corporation, Jeffrey H Ingerman, Robert W Morris, January 24, 1995: US05384499 (18 worldwide citation)

A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to logic array blocks. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes the user's ability to route a selected line t ...