1

2
Stengl Reinhard J, Hammerl Erwin, Mandelman Jack A, Ho Herbert L, Srinivasan Radhika, Short Alvin P: Method of connecting a dram trench capacitor. Siemens, IBM, August 27, 1997: EP0791959-A1 (10 worldwide citation)

In a method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell, the electrical connection (90) is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline s ...


3
Hammerl Erwin, Mandelman Jack A, Ho Herbert L, Shiozawa Junichi, Stengl Reinhard Johannes: Method for forming a buried strap by controlled recrystallisation, in a semiconductor memory device, and semiconductor memory device thereby formed. Ibm, Siemens, Tokyo Shibaura Electric Co, October 23, 1996: EP0739033-A2 (4 worldwide citation)

Forming a coupled capacitor and transistor comprises: (a) forming a trench in a semiconductor substrate; (b) forming an impurity-doped first conductive region by filling the trench with an impurity-doped first conductive material; (c) back etching the impurity-doped first conductive region to a firs ...


4
Hammerl Erwin, Mandelman Jack A, Poschenrieder Bernhard, Short Alvin P, Srinivasan Radhika, Stengl Reinhard J, Ho Herbert L: Trench capacitor dram cell and method of making the same. Siemens, IBM, December 29, 1997: EP0814507-A1 (2 worldwide citation)

Method for forming three-dimensional device structures such as a trench capacitor DRAM cell comprising a second device (370) formed over a first device (315) is disclosed. A layer (350,355) having a single crystalline top surface (350) is formed above the first device (315) to provide the base for f ...


5
Hammerl Erwin, Mandelman Jack A, Short Alvin P, Stengl Reinhard J, Ho Herbert L, Poschenrieder Bernhard, Srinivasan Radhika: Dram cell with trench capacitor. Siemens, IBM, March 10, 1999: EP0901168-A2 (2 worldwide citation)

Method for forming three-dimensional device structures comprising a second device formed over a first device is disclosed. A layer having a single crystalline top surface is formed above the first device to provide the base for forming the active area of the second device.


6
Cheng Kangguo, Ramachandra Deibakaruni, Ho Herbert L, Karl J Reedensu: Structure including trench capacitor array, and method of forming the same (simplified, embedded plate structure and process of the same). Internatl Business Mach Corp &Lt IBM&Gt, September 21, 2006: JP2006-253684 (2 worldwide citation)

PROBLEM TO BE SOLVED: To provides a structure including a trench capacitor array at least part of which is arranged under an embedded oxide layer of an SOI substrate.SOLUTION: Each trench capacitor shares a common unitary embedded capacitor plate including at least part of a first unitary semiconduc ...


7
Ho Herbert L, Srinivasan Radhika, Halle Scott D, Hammerl Erwin, Dobuzinsky David M, Mandelman Jack A, Jaso Mark Anthony: Process for forming a deep trench-type storage node for a dram. Siemens, IBM, September 10, 1997: EP0794567-A2 (1 worldwide citation)

Making a storage node for a deep trench-based DRAM on a semiconductor substrate comprises etching a trench in the substrate, forming a dielectric layer on the sidewall and partly removing this to expose and underlying region of an upper part of the sidewall on which a layer of oxide is grown. Part o ...


8
Hammerl Erwin, Ho Herbert L: Dram trench capacitor with insulating collar. Siemens, IBM, September 10, 1997: EP0794576-A2 (1 worldwide citation)

A method for forming an oxygen-impervious barrier on the oxide collar of a trench capacitor in a DRAM cell. The process consists of etching a shallow trench (33) into the oxide collar which surrounds the polysilicon trench fill (35) and isolating it from the single crystal semiconducting substrate m ...


9
Economikos Laertis, Gruening Ulrike, Ho Herbert L, Radens Carl J, Jammy Ragarao, Hoepfner Joachim, Shen Hua: Dram trench capacitor and method of fabricating the same. Ibm, Siemens, December 8, 1999: EP0962972-A1 (1 worldwide citation)

A storage node for deep trench-based storage capacitor is formed by etching a trench (11) in a surface of a semiconductor substrate (10), forming a layer of dielectric (14) on a sidewall of the trench, partially removing the layer of dielectric material in order to expose an upper portion of the sid ...


10
Bard Karen A, Dobuzinsky David M, Ho Herbert L, Kumar Mahendar, Pendleton Denise: Soi trench capacitor dram cell incorporating a low-leakage floating body array transistor. International Business Machines Corporation, December 1, 2006: TWI267979 (1 worldwide citation)

A DRAM array in an SOI wafer having a uniform BOX layer extending throughout the array eliminates the collar oxide step in processing; connects the buried plates with an implant that, in turn, is connected to a conductive plug extending through the device layer and the box that is biased at ground; ...