1
Yasuhiro Konishi, Takayuki Miyamoto, Takeshi Kajimoto, Hisashi Iwamoto: Synchronous semiconductor memory device. Mitsubishi Denki Kabushiki Kaisha, Lowe Price LeBlanc & Becker, January 24, 1995: US05384745 (277 worldwide citation)

Memory arrays are divided into banks which can be operated independent from each other. Read data storing registers and write data storing registers operating independent from each other are provided for the banks. The memory array is divided into a plurality of small array blocks, local IO lines ar ...


2
Takashi Kubo, Kenichi Yasuda, Hisashi Iwamoto: Memory module system having multiple memory modules. Mitsubishi Denki Kabushiki Kaisha, McDermott Will & Emery, January 8, 2002: US06338113 (148 worldwide citation)

There are provided a memory controller, a plurality of memory modules, and an external data bus common to the plurality of memory modules. The plurality of memory modules each include a plurality of memory chips, a plurality of internal data buses connected between a corresponding memory chip and an ...


3
Yasumitsu Murai, Hisashi Iwamoto, Yasuhiro Konishi, Naoya Watanabe, Seiji Sawada: Synchronous type semiconductor memory device operating in synchronization with an external clock signal. Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering, Lowe Price LeBlanc & Becker, April 4, 1995: US05404338 (132 worldwide citation)

In a synchronous semiconductor memory device, memory arrays (MA) forming activation units each are divided into a plurality of small memory arrays (MK). There are provided local I/O line pairs (LIO) each for two small memory arrays. The global I/O line pairs (GIO) crossing word lines are arranged in ...


4
Yasuhiro Konishi, Hisashi Iwamoto, Takashi Araki, Yasumitsu Murai, Seiji Sawada: Synchronous semiconductor memory device and synchronous memory module. Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering, McDermott Will & Emery, September 29, 1998: US05815462 (99 worldwide citation)

A first clock signal for controlling the inputting of an external signal and for controlling internal operation and a second clock signal for controlling data output are applied to separate clock input nodes, respectively. Data output timing with respect to the first clock signal can be adjusted and ...


5
Yasuhiro Konishi, Takayuki Miyamoto, Takeshi Kajimoto, Hisashi Iwamoto: Synchronous semiconductor memory device. Mitsubishi Denki Kabushiki Kaisha, Lowe Price LeBlanc & Becker, January 14, 1997: US05594704 (67 worldwide citation)

Memory arrays are divided into banks which can be operated independent from each other. Read data storing registers and write data storing registers operating independent from each other are provided for the banks. The memory array is divided into a plurality of small array blocks, local IO lines ar ...


6
Hisashi Iwamoto, Yasuhiro Konishi: Synchronous semiconductor memory device. Mitsubishi Denki Kabushiki Kaisha, Lowe Price LeBlanc & Becker, January 13, 1998: US05708611 (65 worldwide citation)

A refresh control circuit of a DLL circuit responds to an auto refresh detection signal AR and a self refresh detection signal SR to inhibit input of clock signals ECLK and RCLK to a phase comparator and to a voltage control delay circuit. The DLL circuit can be stopped in a mode where an internal c ...


7
Hisashi Iwamoto, Yasumitsu Murai, Yasuhiro Konishi, Naoya Watanabe, Seiji Sawada: Synchronous type semiconductor memory device operating in synchronization with an external clock signal. Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering, Lowe Price LeBlanc & Becker, May 14, 1996: US05517462 (49 worldwide citation)

In a synchronous semiconductor memory device, memory arrays (MA) forming activation units each are divided into a plurality of small memory arrays (MK). There are provided local I/O line pairs (LIO) each for two small memory arrays. The global I/O line pairs (GIO) crossing word lines are arranged in ...


8
Hisashi Iwamoto: Semiconductor device capable of generating highly precise internal clock. Mitsubishi Denki Kabushiki Kaisha, McDermott Will & Emery, December 3, 2002: US06489823 (49 worldwide citation)

A DLL circuit includes a delay line having a configuration with delay stages receiving alternate complementary clock signals ECK and /ECK having an adjusted phase difference therebetween. A capacitor can be used to adjust the phase difference between signals ECK and /ECK to allow the delay line to p ...


9
Hisashi Iwamoto, Yasuhiro Konishi: Voltage control type delay circuit and internal clock generation circuit using the same. Mitsubishi Denki Kabushiki Kaisha, Lowe Price LeBlanc & Becker, March 24, 1998: US05731727 (46 worldwide citation)

A control transistor is connected in parallel with an input transistor of a bias generation circuit in a voltage control delay circuit. A power supply potential Vcc is divided by voltage divider resistors to be applied to the gate of the control transistor. Reduction in the power supply potential Vc ...


10
Nobuyuki Sato, Hisashi Iwamoto: Synchronous semiconductor memory device operable in a plurality of data write operation modes. Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering, McDermott Will & Emery, April 6, 1999: US05892730 (42 worldwide citation)

A synchronous semiconductor memory device can achieve either of a pipelined mode and a prefetch mode with one chip. In accordance with CAS (column address strobe) latency 4 instructing signal MCL4 stored in a mode register, a sequence of generation of control signals from a control signal generating ...