1
Hiroshi Naritomi, Osamu Kobayashi: Output circuit for electronic devices. Fujitsu, Arent Fox Kintner Plotkin & Kahn PLLc, December 11, 2001: US06329842 (2 worldwide citation)

An output circuit that prevents the flow of a leakage current from its output terminal to a power supply is able to accommodate voltage levels higher than the power supply voltage level. The output circuit includes a p-channel MOS transistor connected between the output terminal and a high potential ...


2
Teruyoshi Kondo, Masayuki Takeshige, Sumitaka Hibino, Hayato Isobe, Yukisato Miyazaki, Kunihiro Ohara, Kazuya Taniguchi, Hiroshi Naritomi: Method and apparatus for compactly storing instruction codes. Fujitsu, Staas & Halsey, December 31, 2002: US06502179 (1 worldwide citation)

A processor for performing calculations based on an instruction code, the number of bits of which is not an integer multiple of a byte. The instruction code is divided into higher order bits and lower order bits. The number of the lower order bits is an integer multiple of one byte. A memory stores ...


3
Hiroshi Fukuda, Hiroshi Naritomi: Power supply voltage control circuit device and power supply voltage control method. SOCIONEXT, Arent Fox, September 25, 2018: US10082861

A power supply voltage control circuit device includes a power supply control circuit, a memory, and an arithmetic processing circuit. The power supply control circuit is configured to control a power supply voltage to be applied to a target circuit, and the memory is configured to store a first pro ...


4
Hiroshi Naritomi, Hayato Isobe: Data recovery circuit. Fujitsu Semiconductor, Arent Fox, February 14, 2012: US08117524

A data recovery circuit for recovering data from a parity error without entirely rewriting the data. A write circuit is connected to memory regions including an actual data region and a copy region. A first parity generation circuit writes actual data with even parity to the actual data region. A se ...


5
Hiroshi NARITOMI, Hayato Isobe: Data recovery circuit. Fujitsu, Arent Fox, September 18, 2008: US20080229169-A1

A data recovery circuit for recovering data from a parity error without entirely rewriting the data. A write circuit is connected to memory regions including an actual data region and a copy region. A first parity generation circuit writes actual data with even parity to the actual data region. A se ...


6
Teruyoshi Kondo, Masayuki Takeshige, Sumitaka Hibino, Hayato Isobe, Yukisato Miyazaki, Kunihiro Ohara, Kazuya Taniguchi, Hiroshi Naritomi: Processor and information processing method. Staas & Halsey, February 21, 2002: US20020023205-A1

A processor for performing calculations based on an instruction code, the number of bits of which is not an integer multiple of a byte. The instruction code is divided into higher order bits and lower order bits. The number of the lower order bits is an integer multiple of one byte. A memory stores ...