1
Kenji Sakurada, Hironori Uchikawa: Semiconductor memory device and decoding method. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt L, February 26, 2013: US08385117 (26 worldwide citation)

A memory card decodes three bits of data stored in one memory cell and belonging to different pages, each being a unit of reading, by iterative calculation using probability based on eight threshold voltage distributions. The memory card includes a word line controlling section configured to select ...


2
Mitsuaki Honma, Noboru Shibata, Hironori Uchikawa: Non-volatile semiconductor storage system. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt P C, March 24, 2009: US07508704 (24 worldwide citation)

In a memory cell array, memory cells enabled to store plural-bit data are arranged in matrix. The bit-line control circuit is connected to bit-lines to control the bit-lines. A word line control circuit applies a plural-bit data read voltage as a word line voltage to the word line. The plural-bit da ...


3
Daisuke Takeda, Yoshimasa Egashira, Tsuguhide Aoki, Yasuhiko Tanabe, Kohsuke Harada, Hironori Uchikawa: Wireless communication apparatus. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt P C, May 12, 2009: US07532681 (18 worldwide citation)

Before data is transmitted from a plurality of antennas, a plurality of known symbol sequences are transmitted from these antennas. Each known symbol sequence contains a plurality of known symbols having different subcarrier arrangements. Known symbols transmitted from different antennas have differ ...


4
Tatsuyuki Ishikawa, Mitsuaki Honma, Hironori Uchikawa: Non-volatile semiconductor storage device and non-volatile storage system. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt L, October 4, 2011: US08032810 (15 worldwide citation)

This memory device comprises a word-line control circuit applying a read voltage and a soft-value read voltage as a word line voltage to a word line to generate soft-values. The soft-value read voltage is between an upper limit and a lower limit of each of plural threshold voltage distributions. A l ...


5
Hironori Uchikawa, Tatsuyuki Ishikawa, Mitsuaki Honma: Non-volatile semiconductor memory device. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt L, March 13, 2012: US08136014 (10 worldwide citation)

A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information of N bits (N≧2) in accordance with variations in threshold voltage. A parity data adder circuit adds parity data for error correction to every certain ...


6
Kenji Sakurada, Hironori Uchikawa: Memory system and control method for the same. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt L, August 21, 2012: US08250437 (9 worldwide citation)

A memory system in an embodiment having a host and a memory card, including: a plurality of semiconductor memory cells, each cell being configured to store N-bit coded data based on threshold voltage distributions; an LLR table storage section configured to store a first LLR table that consists of n ...


7
Shinichi Kanno, Hironori Uchikawa: Semiconductor memory device and method of controlling the same. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt L, February 14, 2012: US08117517 (8 worldwide citation)

A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting co ...


8
Mitsuaki Honma, Noboru Shibata, Hironori Uchikawa: Non-volatile semiconductor storage system. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt L, January 18, 2011: US07872910 (7 worldwide citation)

In a memory cell array, memory cells enabled to store plural-bit data are arranged in matrix. The bit-line control circuit is connected to bit-lines to control the bit-lines. A word line control circuit applies a plural-bit data read voltage as a word line voltage to the word line. The plural-bit da ...


9
Hironori Uchikawa, Kenji Sakurada: Controller and non-volatile semiconductor memory device. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt L, April 3, 2012: US08149623 (7 worldwide citation)

A controller includes a generation unit configured to aggregate comparison results between second threshold voltage levels held in the memory cells and predetermined third threshold voltage levels, and generate a histogram of the second threshold voltage levels, an estimation unit configured to esti ...


10
Hironori Uchikawa, Tatsuyuki Ishikawa, Mitsuaki Honma: Non-volatile semiconductor memory device. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt L, December 13, 2011: US08078940 (6 worldwide citation)

A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information in accordance with variations in threshold voltage. A likelihood calculator has a plurality of likelihood calculation algorithms for deriving a likeli ...