1
Hidekazu Matsumoto, Tadaaki Bandoh, Hideo Maejima: Data processing unit with pipelined operands. Hitachi, Antonelli Terry & Wands, June 12, 1984: US04454578 (126 worldwide citation)

A data processing unit for executing variable length instructions in which operand specifiers for specifying addressing modes of operands are independent from operation codes for ascertaining operations is disclosed. An instruction fetch unit includes an instruction buffer for prefetching and retain ...


2
Yasushi Fukunaga, Tadaaki Bandoh, Hidekazu Matsumoto, Ryosei Hiraoka, Jushi Ide, Takeshi Kato, Tetsuya Kawakami: Shared virtual address translation unit for a multiprocessor system. Hitachi, Hitachi Engineering, Antonelli Terry & Wands, November 6, 1984: US04481573 (110 worldwide citation)

A virtual storage data processing system having an address translation unit shared by a plurality of processors, located in a memory control unit connected to a main memory is disclosed. One of the plurality of processors is a job processor which accesses the main memory with a virtual address to ex ...


3
Yasushi Fukunaga, Tadaaki Bandoh, Ryosei Hiraoka, Hidekazu Matsumoto, Jushi Ide, Tetsuya Kawakami: Bus selection control in a data transmission apparatus for a multiprocessor system. Hitachi, Hitachi Engineering, Antonelli Terry & Wands, June 11, 1985: US04523272 (63 worldwide citation)

In a multiprocessor system having a main memory and a plurality of processors connected through common address bus, data bus and answer bus for data transfer, a data transmission apparatus is provided for each of the main memory and the processors and includes bus request control lines for transferr ...


4
Kenji Hirose, Tadaaki Bandoh, Hidekazu Matsumoto, Shinichiro Yamaguchi, Hirokazu Hirayama, Hiroaki Nakanishi: Apparatus for performing floating point arithmetic operations and rounding the result thereof. Hitachi, Hitachi Engineering, Antonelli Terry & Wands, June 13, 1989: US04839846 (49 worldwide citation)

An operation unit capable of performing round processing at a high speed in a floating point operation. A circuit for detecting an overflow on the condition of a signal representing all 1's in an output of a mantissa shifter and a signal representing round-up, a carry look-ahead circuit and a circui ...


5
Kenji Hirose, Tadaaki Bandoh, Hidekazu Matsumoto, Shinichiro Yamaguchi, Hirokazu Hirayama, Hiroaki Nakanishi: Bit slice multiplication circuit. Hitachi, Hitachi Engineering, Antonelli Terry & Wands, March 7, 1989: US04811269 (49 worldwide citation)

A bit slice multiplication circuit operating to slice a multiplier, produce products for the sliced multipliers and a multiplicand and sum the products to obtain the multiplication result. The circuit includes a slicing unit for slicing the multiplicand, multiplying units corresponding in number to ...


6
Yasushi Fukunaga, Tadaaki Bandoh, Kotaro Hirasawa, Hidekazu Matsumoto, Jushi Ide, Takeshi Katoh, Hiroaki Nakanishi, Tetsuya Kawakami, Ryosei Hiraoka: Central processing unit for executing instructions of variable length having end information for operand specifiers. Hitachi, Hitachi Engineering, Antonelli Terry & Wands, July 16, 1985: US04530050 (42 worldwide citation)

A central processing unit for executing instructions of variable length in which an operand specifier for specifying the addressing mode of an operand is independent of an operation code for ascertaining the kind of an operation and the number of operands. Each operand specifier is formed of one or ...


7
Hideo Maejima, Ikuro Masuda, Hidekazu Matsumoto, Shyoichi Miyazawa: Input/output control device with memory device for storing variable-length data and method of controlling thereof. Hitachi, Antonelli Terry & Wands, June 11, 1985: US04523276 (31 worldwide citation)

An input/output control device stores variable-length data in a memory device at a high storage efficiency and without reducing the speed of data processing. The data stored in a memory are read out in the form of data of a fixed word length and then processed, the data having been processed are sto ...


8
Takao Kobayashi, Shigeo Abe, Tadaaki Bandoh, Masao Takatoo, Hidekazu Matsumoto, Hideyuki Hara: Floating point data adder. Hitachi, Hitachi Engineering, Antonelli Terry & Wands, February 17, 1987: US04644490 (27 worldwide citation)

A pipelined adder for adding or subtracting two floating point input data each expressed by a sign data, an exponent data and a mantissa expressed in a sign-magnitude format, in accordance with an external operation mode designation signal to produce a floating point sum or difference data in a sign ...


9
Shinichiro Yamaguchi, Hidekazu Matsumoto, Tadaaki Bandoh, Hirokazu Hirayama, Takayuki Morioka, Soichi Takaya, Yukio Kawamoto, Jushi Ide, Yoshihiro Miyazaki: Suspended instruction restart processing system based on a checkpoint microprogram address. Hitachi, Antonelli Terry Stout & Kraus, March 26, 1991: US05003458 (23 worldwide citation)

Method and apparatus for instruction restart processing in a microprogram - controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is ...


10
Hidekazu Matsumoto, Tadaaki Bandoh, Ryosei Hiraoka, Takayuki Morioka, Yoshihiro Miyazaki: Microprogrammed control data processing apparatus in which operand source and/or operand destination is determined independent of microprogram control. Hitachi, Antonelli Terry & Wands, February 21, 1989: US04807113 (20 worldwide citation)

A microprogram controlled data processing apparatus executes multi-operand instructions in which one or more operand specifiers are provided for specifying the addressing for each operand independently from the operation code of the instruction. An instruction execution unit receives a top address o ...