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Edward Aung, Henry Lui, Paul Butler, John Turner, Rakesh Patel, Chong Lee: Clock data recovery circuitry associated with programmable logic device circuitry. Altera Corporation, Fish & Neave IP Group Ropes & Gray, Robert R Jackson, Michael J Chasan, June 5, 2007: US07227918 (29 worldwide citation)

A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circu ...


2
Malik Kabani, Henry Lui: Programmable logic resource with data transfer synchronization. Altera Corporation, Fish & Neave IP Group Ropes & Gray, Evelyn C Mak, February 21, 2006: US07003423 (20 worldwide citation)

A more time-efficient and area-efficient approach is provided to synchronize the transfer of data into programmable logic resources. A programmable logic resource core clock and a reset signal are routed to a reset register that controls the reset of a dynamic phase alignment circuit and a data real ...


3
Ramanand Venkata, Chong H Lee, Henry Lui: Digital phase locked loop circuitry and methods. Altera Corporation, Fish & Neave IP Group Ropes & Gray, Robert R Jackson, November 21, 2006: US07138837 (14 worldwide citation)

Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and oper ...


4
Arch Zaliznyak, William Bereza, Henry Lui, Chong Lee, Rakesh Patel: Circuits and techniques for conditioning differential signals. Altera Corporation, Fish & Neave IP Group of Ropes & Gray, Andrew Van Court, January 10, 2006: US06985021 (7 worldwide citation)

Circuitry is provided that conditions a differential input signal such that when the signal is received by a multi-standard differential input buffer, the buffer is able to process the conditioned signal without pronounced increases in propagation delay, thereby keeping signal jitter to a minimum. T ...


5
Edward Aung, Henry Lui, Paul Butler, John Turner, Rakesh Patel, Chong Lee: Clock data recovery circuitry associated with programmable logic device circuitry. Altera Corporation, Ropes & Gray, March 23, 2010: US07684532 (4 worldwide citation)

A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circu ...


6
Edward Aung, Henry Lui, Paul Butler, John Turner, Rakesh Patel, Chong Lee: Clock data recovery circuitry associated with programmable logic device circuitry. Altera Corporation, Ropes & Gray, Robert R Jackson, Michael J Chasan, February 19, 2008: US07333570 (4 worldwide citation)

A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circu ...


7
Edward Aung, Henry Lui, Paul Butler, John Turner, Rakesh Patel, Chong Lee: Clock data recovery circuitry associated with programmable logic device circuitry. Fish & Neave, October 25, 2001: US20010033188-A1 (4 worldwide citation)

A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circu ...


8
Ramanand Venkata, Henry Lui, Arch Zaliznyak: Techniques for aligning and reducing skew in serial data signals. Altera Corporation, Steven J Cahill, March 31, 2015: US08994425 (2 worldwide citation)

A circuit includes first and second aligner circuits and a deskew circuit. The first aligner circuit is operable to align a first input serial data signal with a control signal to generate a first aligned serial data signal. The second aligner circuit is operable to align a second input serial data ...


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