1
Harold L McFarland, David R Stiles, Korbin S Van Dyke, Shrenik Mehta, John G Favor, Dale R Greenley, Robert A Cargnoni: Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags. Nexgen Microsystems, Townsend and Townsend Khourie and Crew, July 6, 1993: US05226126 (369 worldwide citation)

A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The units execute the operations and report terminat ...


2
Harold L McFarland, David R Stiles, Korbin S Van Dyke, Shrenik Mehta, John Gregory Favor, Dale R Greenley, Robert A Cargnoni: Method and apparatus for debugging an integrated circuit. Advanced Micro Devices, B Noël Kivlin, Conley Rose & Tayon PC, December 24, 2002: US06499123 (154 worldwide citation)

An integrated circuit having a normal mode for operating under normal operating conditions and a debug mode for operating to test and debug the integrated circuit. The integrated circuit includes a plurality of output pins that carry a first plurality of signals in the normal mode and carry a second ...


3
Allen W Roberts, Harold L McFarland Jr, Harlan Lau: High speed data bus system. Elxsi, Townsend and Townsend, November 6, 1984: US04481625 (146 worldwide citation)

In a high speed data bus system, each functional unit has an associated port which operates to accept all related information that makes up a communication, or if this cannot be done, to accept none of the information. More particularly, an information transfer, depending on its nature, may comprise ...


4
Harold L McFarland, David R Stiles, Korbin S Van Dyke, Shrenik Mehta, John G Favor, Dale R Greenley, Robert A Cargnoni: Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts. NexGen, Townsend and Townsend Khourie and Crew, August 15, 1995: US05442757 (103 worldwide citation)

A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The units execute the operations and report terminat ...


5
Harold L McFarland, David R Stiles, Korbin S Van Dyke, Shrenik Mehta, John Gregory Favor, Dale R Greenley, Robert A Cargnoni: Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructions. Advanced Micro Devices, Townsend and Townsend and Crew, June 16, 1998: US05768575 (95 worldwide citation)

A pipeline control system for implementing a virtual architecture having complex instruction set is distributed over RISC-like semi-autonomous functional units in a processor. Decoder logic fetches instructions of the target architecture and translates them into simpler RISC-like operations. These o ...


6
Harold L McFarland, Allen P Ho: Crossing transfers for maximizing the effective bandwidth in a dual-bus architecture. Advanced Micro Devices, Townsend and Townsend and Crew, May 6, 1997: US05627976 (78 worldwide citation)

A dual-bus architecture that includes a high-speed system bus, called the NexBus (20), and a slower peripheral bus, called the alternate bus or AB (25). The NexBus and AB are coupled by control logic (45) which includes an arbiter (50) and an alternate bus interface (ABI) (60). The ABI is treated as ...


7
Harold L McFarland: Voltage-controlled delay element with programmable delay. NexGen, Townsend and Townsend and Crew, November 5, 1996: US05572159 (65 worldwide citation)

A voltage-controlled delay element utilizes a current-starved inverter configuration with a feedback path that ensures a rapid discharge of the storage node to ground once the desired delay time has elapsed. The circuit comprises a circuit path for charging the storage node (preferably rapidly), a f ...


8
Harold L McFarland, Allen P Ho: Crossing transfers for maximizing the effective bandwidth in a dual-bus architecture. NexGen, Townsend and Townsend Khourie and Crew, May 9, 1995: US05414820 (63 worldwide citation)

A dual-bus architecture that includes a high-speed system bus, called the NexBus (20), and a slower peripheral bus, called the alternate bus or AB (25). The NexBus and AB are coupled by control logic (45) which includes an arbiter (50) and an alternate bus interface (ABI) (60). The ABI is treated as ...


9
Harold L McFarland, David R Stiles, Korbin S Van Dyke, Shrenik Mehta, John Gregory Favor, Dale R Greenley, Robert A Cargnoni: Semi-autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for speculative and out-of-order execution of complex instructions. Advanced Micro Devices, Townsend and Townsend and Crew, July 14, 1998: US05781753 (50 worldwide citation)

A pipeline control system for implementing a virtual architecture having a complex instruction set is distributed over RISC-like semi-autonomous functional units in a processor. Decoder logic fetches instructions of the target architecture and translates them into simpler RISC-like operations. These ...


10
Harold L McFarland Jr: Improved terminator for high speed data bus. ELXSI, Townsend & Townsend, June 17, 1986: US04595923 (50 worldwide citation)

A very high speed data bus system for communication among the various functional units that may constitute a large computer system. The bus communication medium comprises a number of line pairs on the backplane, and the bus system comprises a bus control unit for arbitrating requests from a pluralit ...