1
Kuljit S Bains, Navneet Dour, Hany Fahmy, George Vergis, Christopher E Cox: Method and apparatus to calibrate DRAM on resistance (Ron) and on-die termination (ODT) values over process, voltage and temperature (PVT) variations. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 7, 2008: US07432731 (21 worldwide citation)

An embodiment may comprise memory with a memory array, a resistor coupled to a reference voltage, on die termination circuitry coupled with the resistor, and an input coupled to the on die termination circuitry and coupled with the memory array, the input to receive a calibration command to stop use ...


2
Christopher Cox, George Vergis, Hany Fahmy, Hideo Oie: Polarity driven dynamic on-die termination. Intel Corporation, Philip A Pedigo, May 13, 2008: US07372293 (20 worldwide citation)

Embodiments of the invention are generally directed to systems, methods, and apparatuses for polarity driven on-die termination. In some embodiments, an integrated circuit includes an input/output (I/O) circuit to receive a command and an on-die termination (ODT) pin to receive one or more ODT signa ...


3
Zhi Cui, Alan Blackburn, Hany Fahmy: Network selection architecture. AT&T Intellectual Property I, Hartman & Citrin, June 28, 2016: US09380646 (2 worldwide citation)

A user equipment device intelligent network selection architecture is provided that enables service provider policy driven dynamic intelligent network selection of a radio technology for user traffic delivery. The network selection is based on radio network conditions, user subscription profile, and ...


4
Christopher Cox, George Vergis, Hany Fahmy, Hideo Oie: Polarity driven dynamic on-die termination. Intel Corporation, Intel Corporation, c o INTELLEVATE, June 7, 2007: US20070126463-A1

Embodiments of the invention are generally directed to systems, methods, and apparatuses for polarity driven on-die termination. In some embodiments, an integrated circuit includes an input/output (I/O) circuit to receive a command and an on-die termination (ODT) pin to receive one or more ODT signa ...


5
Kuljit S Bains, Navneet Dour, Hany Fahmy, George Vergis, Christopher E Cox: Method to calibrate DRAM Ron and ODT values over PVT. Marger Johnson & Mccollom PC, January 11, 2007: US20070007992-A1

An embodiment may comprise memory with a memory array, a resistor coupled to a reference voltage, on die termination circuitry coupled with the resistor, and an input coupled to the on die termination circuitry and coupled with the memory array, the input to receive a calibration command to stop use ...


6
Hideo Oie, Hany Fahmy, Christopher Cox, George Vergis: Memory system with dynamic termination. Intel Corporation, c o INTELLEVATE, October 25, 2007: US20070247185-A1

The termination impedance of a memory agent may be selected dynamically. A transmission line may be simultaneously terminated with a first impedance at first memory agent and a different impedance at a second memory agent. A memory agent may have a terminator with at least two termination values and ...


7
Christopher E Cox, Hany Fahmy, Hideo Oie: Per byte lane dynamic on-die termination. Intel Corporation, Intel Corporation, c o INTELLEVATE, August 21, 2008: US20080197877-A1

Embodiments of the invention are generally directed to systems, methods, and apparatuses for per byte lane dynamic on-die termination. In some embodiments, an integrated circuit includes logic to independently program at least one on-die termination (ODT) value for each of a plurality of integrated ...


8
Christopher Cox, George Vergis, Hany Fahmy, Hideo Oie: Polarity driven dynamic on-die termination. Intel, wu shaodun wang yang, February 16, 2011: CN201010267882

Embodiments of the invention are generally directed to systems, methods, and apparatuses for polarity driven on-die termination. In some embodiments, an integrated circuit includes an input/output (I/O) circuit to receive a command and an on-die termination (ODT) pin to receive one or more ODT signa ...