1
Bin Yu, Judy Xilin An, Cyrus E Tabery, Haihong Wang: Method for forming multiple structures in a semiconductor device. Advanced Micro Devices, Harrity & Snyder, March 16, 2004: US06706571 (477 worldwide citation)

A method of forming multiple structures in a semiconductor device includes depositing a film over a conductive layer, etching a trench in a portion of the film and forming adjacent the sidewalls of the trench. The film may then be etched, followed by an of the conductive layer to form the structures ...


2
Zoran Krivokapic, Judy Xilin An, Srikanteswara Dakshina Murthy, Haihong Wang, Bin Yu: Narrow fin FinFET. Advanced Micro Devices, Harrity & Snyder, July 26, 2005: US06921963 (212 worldwide citation)

A narrow channel FinFET is described herein with a narrow channel width. A protective layer may be formed over the narrow channel, the protective layer being wider than the narrow channel.


3
Ming Ren Lin, Jung Suk Goo, Haihong Wang, Qi Xiang: FinFET device incorporating strained silicon in the channel region. Advanced Micro Devices, Foley & Lardner, October 5, 2004: US06800910 (176 worldwide citation)

A FinFET device employs strained silicon to enhance carrier mobility. In one method, a FinFET body is patterned from a layer of silicon germanium (SiGe) that overlies a dielectric layer. An epitaxial layer of silicon is then formed on the silicon germanium FinFET body. A strain is induced in the epi ...


4
Matthew S Buynoski, Srikanteswara Dakshina Murthy, Cyrus E Tabery, Haihong Wang, Chih Yuh Yang, Bin Yu: Method for forming fins in a FinFET device using sacrificial carbon layer. Advanced Micro Devices, Harrity & Snyder L, November 11, 2003: US06645797 (170 worldwide citation)

A method for forming a fin in a semiconductor device that includes a substrate, an insulating layer formed on the substrate, and a conductive layer formed on the insulating layer, includes forming a carbon layer over the conductive layer and forming a mask over the carbon layer. The method further i ...


5
Matthew S Buynoski, Judy Xilin An, Haihong Wang, Bin Yu: Double spacer FinFET formation. Advanced Micro Devices, Harrity & Snyder, March 23, 2004: US06709982 (149 worldwide citation)

A method for forming a group of structures in a semiconductor device includes forming a conductive layer on a substrate, where the conductive layer includes a conductive material, and forming an oxide layer over the conductive layer. The method further includes etching at least one opening in the ox ...


6
Shibly S Ahmed, Haihong Wang, Bin Yu: Double gate semiconductor device having separate gates. Advanced Micro Devices, Harrity & Snyder, August 26, 2003: US06611029 (147 worldwide citation)

A semiconductor device may include a substrate and an insulating layer formed on the subtrate. A fin may be formed on the insulating layer and may include a number of side surfaces and a top surface. A first gate may be formed on the insulating layer proximate to one of the number of side surfaces o ...


7
Bin Yu, Haihong Wang: Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device. Advanced Micro Devices, Harrity & Snyder, July 20, 2004: US06764884 (122 worldwide citation)

A method of manufacturing a FinFET device includes forming a fin structure on an insulating layer. The fin structure includes a conductive fin. The method also includes forming source/drain regions and forming a dummy gate over the fin. The dummy gate may be removed and the width of the fin in the c ...


8
Olov B Karlsson, HaiHong Wang, Bin Yu, Zoran Krivokapic, Qi Xiang: Shallow trench isolation (STI) region with high-K liner and method of formation. Advanced Micro Devices, Renner Otto Boisselle & Sklar, December 2, 2003: US06657276 (102 worldwide citation)

A shallow trench isolation region formed in a layer of semiconductor material. The shallow trench isolation region includes a trench formed in the layer of semiconductor material, the trench being defined by sidewalls and a bottom; a liner within the trench formed from a high-K material, the liner c ...


9
Haihong Wang, Joong Jeon: Method of fabricating transistor having a single crystalline gate conductor. Advanced Micro Devices, Foley & Lardner, September 16, 2003: US06620671 (101 worldwide citation)

A method of manufacturing an integrated circuit on a substrate provides a gate structure including single crystalline material. The method can provide a first amorphous or polycrystalline semiconductor layer above a top surface of the substrate and patterning the first amorphous semiconductor layer ...


10
Qi Xiang, Eric N Paton, Haihong Wang: Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication. Advanced Micro Devices, Foley & Lardner, March 9, 2004: US06703648 (95 worldwide citation)

A strained silicon p-type MOSFET utilizes a strained silicon channel region formed on a silicon germanium substrate. Silicon germanium regions are formed to the silicon germanium layer adjacent to ends of the strained silicon channel region, and shallow source and drain extensions are implanted in t ...



Click the thumbnails below to visualize the patent trend.