1
Hagop A Nazarian: Multiple level programming in a non-volatile memory device. Micron Technology, Leffert Jay & Polglaze P A, May 22, 2007: US07221592 (83 worldwide citation)

The programming method of the present invention minimizes program disturb by initially programming cells on the same wordline with the logical state having the highest threshold voltage. The remaining cells on the wordline are programmed to their respective logical states in order of decreasing thre ...


2
Hagop A Nazarian: Boosted substrate/tub programming for flash memories. Micron Technology, Leffert Jay & Polglaze PA, December 20, 2005: US06977842 (53 worldwide citation)

A boosted substrate tub/substrate floating gate memory cell programming process is described that applies a voltage to the substrate or substrate “tub” of a NAND Flash memory array to precharge a channel of carriers within the floating gate memory cells prior to applying a high gate programming volt ...


3
Dzung H Nguyen, Benjamin Louie, Hagop A Nazarian, Aaron Yip, Jin Man Han: Programming memory devices. Micron Technology, Leffert Jay & Polglaze P A, September 11, 2007: US07269066 (52 worldwide citation)

A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory c ...


4
Dzung H Nguyen, Benjamin Louie, Hagop A Nazarian, Aaron Yip, Jin Man Han: Programming memory devices. Micron Technology, Leffert Jay & Polglaze P A, March 18, 2008: US07345924 (52 worldwide citation)

A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory c ...


5
Hagop A Nazarian: Apparatus and method for nonvolatile configuration circuit. Cypress Semiconductor, Blakely Sokoloff Taylor & Zafman, April 14, 1998: US05740106 (37 worldwide citation)

A configuration circuit includes a plurality of configuration cells where each configuration cell has (a) a nonvolatile pull-up cell coupled to an output node and for coupling to a first power supply voltage, and (b) a nonvolatile pull-down cell coupled to the nonvolatile pull-up cell and to the out ...


6
Hagop A Nazarian: Boosted substrate/tub programming for flash memories. Micron Technology, Leffert Jay & Polglaze PA, December 12, 2006: US07149124 (27 worldwide citation)

A boosted substrate tub/substrate floating gate memory cell programming process is described that applies a voltage to the substrate or substrate “tub” of a NAND Flash memory array to precharge a channel of carriers within the floating gate memory cells prior to applying a high gate programming volt ...


7
Hagop A Nazarian: Non-volatile memory device and method having bit-state assignments selected to minimize signal coupling. Micron Technology, Dorsey & Whitney, November 25, 2008: US07457155 (25 worldwide citation)

A non-volatile memory device programs memory cells in each row in a manner that minimizes the coupling of spurious signals. A control logic unit programs the cells in a row using a set of bit state assignments chosen by evaluating data that are to be written to the cells in the row. The control logi ...


8
Hagop A Nazarian: Flash memory array using adjacent bit line as source. Micron Technology, Leffert Jay & Polglaze P A, April 10, 2007: US07203092 (18 worldwide citation)

A memory array having a plurality of flash memory cells arranged in rows and columns. A plurality of bit lines couple the columns such that alternate bit lines of the plurality of bit lines are adapted to operate as either source lines or bit lines in response to bit line selection and biasing.


9
Hagop A Nazarian: NAND flash depletion cell structure. Micron Technology, Leffert Jay & Polglaze P A, November 25, 2008: US07457156 (16 worldwide citation)

NAND architecture Flash memory strings, memory arrays, and memory devices are described that utilize depletion mode floating gate memory cells. Depletion mode floating gate memory cells allow for increased cell current through lower channel rds resistance and decreased “narrow width” effect, allowin ...


10
Hagop A Nazarian: Serial transistor-cell array architecture. Micron Technology, Dickstein Shapiro, October 23, 2007: US07286378 (15 worldwide citation)

A memory device having memory cells in which a single access transistor controls the grounding of at least four storage elements, such as resistive storage elements, for purposes of reading the respective logical states of the storage elements. Unique sensing techniques are provided to sense the sta ...