1
Robert Dawson, Mark W Michael, Basab Bandyopadhyay, H Jim Fulford Jr, Fred N Hause, William S Brennan: Substantially planar semiconductor topography using dielectrics and chemical mechanical polish. Advanced Micro Devices, Kevin L Conley Rose & Tayon Daffer, December 15, 1998: US05850105 (154 worldwide citation)

A method for forming a multilevel interconnect structure having a globally planarized upper surface. Dielectrics are deposited upon a semiconductor to minimize pre-existing disparities in topographical height and to create an upper surface topography having a polish rate greater than that of lower r ...


2
H Jim Fulford Jr: Method of making IGFETs in densely and sparsely populated areas of a substrate. Advanced Micro Devices, David M Sigmond, Skjerven Morrill MacPherson Franklin & Friel, August 4, 1998: US05789300 (125 worldwide citation)

A method of making IGFETs in densely and sparsely populated areas of a substrate is disclosed. The method includes providing a semiconductor substrate with first and second regions, forming a gate material over the first and second regions, forming a photoresist layer over the gate material, irradia ...


3
Robert Dawson, H Jim Fulford Jr, Mark I Gardner, Frederick N Hause, Mark W Michael, Bradley T Moore, Derick J Wristers: Method and apparatus for in situ anneal during ion implant. Advanced Micro Devices, Ken J Koestner, Margaret M Kelton, Skjerven Morrill MacPherson L, August 29, 2000: US06111260 (101 worldwide citation)

During a semiconductor substrate ion implant process thermal energy is supplied to raise the temperature of the semiconductor wafer. The increased temperature of the semiconductor wafer during implantation acts to anneal the implanted impurities or dopants in the wafer, reducing impurity diffusion a ...


4
Fred N Hause, Basab Bandyopadhyay, Robert Dawson, H Jim Fulford Jr, Mark W Michael, William S Brennan: Dissolvable dielectric method. Advanced Micro Devices, Kevin L Conley Rose & Tayon Daffer, September 14, 1999: US05953626 (91 worldwide citation)

A fabrication process that produces an air gap dielectric in which a multi-level interconnect structure is formed upon a temporary supporting material. The temporary material is subsequently dissolved away leaving behind an intralevel and an interlevel dielectric comprised of air. In one embodiment ...


5
H Jim Fulford Jr, Robert Dawson, Mark I Gardner, Frederick N Hause, Mark W Michael, Bradley T Moore, Derick J Wristers: Method of channel doping using diffusion from implanted polysilicon. Advanced Micro Devices, Ken J Koestner, Skjerven Morrill MacPherson Franklin & Friel, June 29, 1999: US05918129 (86 worldwide citation)

A method of doping an integrated circuit device channel in a semiconductor substrate laterally enclosed by an isolation structure is disclosed. The method includes steps of forming a thin oxide layer overlying the integrated circuit device channel and the isolation structure, depositing a polysilico ...


6
Mark I Gardner, H Jim Fulford Jr: Separately optimized gate structures for n-channel and p-channel transistors in an integrated circuit. Advanced Micro Devices, Kevin L Daffer, Conley Rose & Tayon P C, July 3, 2001: US06255698 (86 worldwide citation)

An integrated circuit containing separately optimized gate structures for n-channel and p-channel transistors is provided and formed. Original gate structures for both n-channel and p-channel transistors are patterned over appropriately-doped active regions of a semiconductor substrate. Protective d ...


7
Frederick N Hause, Robert Dawson, H Jim Fulford Jr, Mark I Gardner, Mark W Michael, Bradley T Moore, Derick J Wristers: Method of making NMOS and PMOS devices with reduced masking steps. Advanced Micro Devices, Ken J Koestner Esq, Skjerven Morrill MacPherson Franklin & Friel, May 9, 2000: US06060345 (85 worldwide citation)

A method of making NMOS and PMOS devices with reduced masking steps is disclosed. The method includes providing a semiconductor substrate with a first active region of first conductivity type and a second active region of second conductivity type, forming a gate material over the first and second ac ...


8
H Jim Fulford Jr, Robert Dawson, Fred N Hause, Basab Bandyopadhyay, Mark W Michael, William S Brennan: Method of formation of an air gap within a semiconductor dielectric by solvent desorption. Advanced Micro Devices, Kevin L Conley Rose & Tayon Daffer, June 2, 1998: US05759913 (75 worldwide citation)

A dielectric material is provided having air gaps which form during dielectric deposition between interconnects. The dielectric is deposited in interconnect-spaced geometries which have certain aspect ratios and which are exposed at the bottom of the geometries to a hygroscopic dielectric. During de ...


9
Mark I Gardner, Fred N Hause, H Jim Fulford Jr: CMOS integrated circuit formed by using removable spacers to produce asymmetrical NMOS junctions before asymmetrical PMOS junctions for optimizing thermal diffusivity of dopants implanted therein. Advanced Micro Devices, Kevin L Conley Rose & Tayon Daffer, November 17, 1998: US05837572 (74 worldwide citation)

An integrated circuit is provided having both NMOS transistors and PMOS transistors. The NMOS transistor junction regions are preferably formed before the PMOS transistor junction regions with pre-defined anneal temperatures applied after select implant steps. Both the NMOS and PMOS transistor junct ...


10
Basab Bandyopadhyay, H Jim Fulford Jr, Robert Dawson, Fred N Hause, Mark W Michael, William S Brennan: Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines. Advanced Micro Devices, Kevin L Conley Rose & Tayon Daffer, October 27, 1998: US05827776 (70 worldwide citation)

A multilevel interconnect structure is provided. The multilevel interconnect structure includes at least three levels of interconnect (conductors) formed according to one exemplary embodiment. Two of the three levels of conductors are staggered from each other in separate vertical and horizontal pla ...