1
Kenneth D Abramson, H Bruce Butts Jr, David A Orbits: Affinity scheduling of processes on symmetric multiprocessing systems. Digital Equipment Corporation, Christensen O Connor Johnson & Kindness, April 9, 1996: US05506987 (123 worldwide citation)

A method of scheduling processes on a symmetric multiprocessing system that maintains process-to-CPU affinity without introducing excessive idle time is disclosed. When a new process is assigned, the process is identified as young and small, given a migtick value and assigned to a specific CPU. If t ...


2
H Bruce Butts Jr, David A Orbits, Kenneth D Abramson: Coupled memory multiprocessor computer system including cache coherency management protocols. Digital Equipment Corporation, Christensen O Connor Johnson & Kindness, April 12, 1994: US05303362 (116 worldwide citation)

A coherent coupled memory multiprocessor computer system that includes a plurality of processor modules (11a, 11b . . . ), a global interconnect (13), an optional global memory (15) and an input/output subsystem (17,19) is disclosed. Each processor module (11a, 11b . . . ) includes: a processor (21) ...


3
David A Orbits, Kenneth D Abramson, H Bruce Butts Jr: Memory management method for coupled memory multiprocessor systems. Digital Equipment Corporation, Christensen O Connor Johnson & Kindness, August 17, 1993: US05237673 (75 worldwide citation)

A method of managing the memory of a CM multiprocessor computer system is disclosed. A CM multiprocessor computer system includes: a plurality of CPU modules 11a . . . 11n to which processes are assigned; one or more optional global memories 13a . . . 13n; a storage medium 15a, 15b . . . 15n; and a ...


4
H Bruce Butts Jr, James N Leahy, Richard B Gillett Jr: Bus event monitor. Digital Equipment Corporation, Arthur W Fisher, Denis G Maloney, Lindsay G McGuinness, June 20, 1995: US05426741 (59 worldwide citation)

A monitor for monitoring the occurrence of events on the bus (15) of a multiprocessor computer system. The bus event monitor (BEM) includes a dedicated BEM processor (23) and an event counter subsystem (25). During each bus cycle, the BEM (21) captures and interprets the packet of data being transmi ...


5
Kenneth D Abramson, David A Orbits, H Bruce Butts Jr: Adaptive memory management method for coupled memory multiprocessor systems. Digital Equipment Corporation, Christensen O Connor Johnson & Kindness, December 7, 1993: US05269013 (56 worldwide citation)

An adaptive memory management method for coupled memory multiprocessor computer systems is disclosed. In a coupled memory multiprocessor system all the data and stack pages of processes assigned to individual multiprocessors are, preferably, located in a memory region coupled to the assigned process ...


6
H Bruce Butts Jr, David N Cutler, Peter C Schnorr, Robert T Short: Central processing unit for a digital computer. Digital Equipment Corporation, Christensen O Connor Johnson & Kindness, April 29, 1986: US04586130 (33 worldwide citation)

A central processing unit for a digital computer has a central memory unit connected to a system bus. A data path unit decodes variable length microinstructions that are stored in the central memory unit and that include an operation code and one or more operand specifiers, issuing a microaddress of ...


7
David A Orbits, Kenneth D Abramson, H Bruce Butts Jr: Enhanced cache operation with remapping of pages for optimizing data relocation from addresses causing cache misses. Digital Equipment Corporation, Denis G Maloney, Arthur W Fisher, May 13, 1997: US05630097 (29 worldwide citation)

A computer system executing virtual memory management and having a cache is operated in a manner to reduce cache misses by remapping pages of physical memory from which cache misses are detected. The method includes detecting cache misses, as by observing cache fill operations on the system bus, and ...


8
H Bruce Butts Jr, David N Cutler, Peter C Schnorr, Robert T Short: Central processing unit for a digital computer. Digital Equipment Corporation, Arnold White & Durkee, March 14, 1989: US04812971 (11 worldwide citation)

A central processing unit for a digital computer. In one embodiment, the central processing unit comprises a plurality of pointer registers that may be used during instruction execution to directly address other registers. In a second embodiment, the central processing unit comprises a size register ...


9
H Bruce Butts Jr, David N Cutler, Peter C Schnorr, Robert T Short: Central processing unit for a digital computer. Digital Equipment Corporation, Arnold White & Durkee, January 9, 1990: US04893235 (9 worldwide citation)

A central processing unit for a digital computer. In one embodiment, the central processing unit comprises a plurality of pointer registers that may be used during instruction execution to directly address other registers. In a second embodiment, the central processing unit comprises a size register ...