1
Ka Hing Fung, H Bernhard Pogge: Three-dimensional chip stacking assembly. International Business Machines Corporation, H Daniel Schnurmann, March 12, 2002: US06355501 (381 worldwide citation)

An assembly consisting of three dimensional stacked SOI chips, and a method of forming such integrated circuit assembly, each of the SOI chips including a handler making mechanical contact to a first metallization pattern making electrical contact to a semiconductor device. The metalized pattern, in ...


2
H Bernhard Pogge, Roy Yu, Chandrika Prasad, Chandrasekhar Narayan: Chip and wafer integration process using vertical connections. International Business Machines Corporation, Jay H Anderson, July 29, 2003: US06599778 (315 worldwide citation)

A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned a ...


3
H Bernhard Pogge, Roy Yu: Three-dimensional device fabrication method. International Business Machines Corporation, Lisa U Jaklitsch, April 8, 2008: US07354798 (88 worldwide citation)

A method is described for fabricating a three-dimensional integrated device including a plurality of vertically stacked and interconnected wafers. Wafers (1, 2, 3) are bonded together using bonding layers (26, 36) of thermoplastic material such as polyimide; electrical connections are realized by vi ...


4
H Bernhard Pogge: Process for precision alignment of chips for mounting on a substrate. International Business Machines Corporation, Jay H Anderson, August 29, 2000: US06110806 (65 worldwide citation)

A method is described for fabricating a module having a chip attached to a carrier substrate, wherein a guide substrate transparent to ablation radiation is used. A removable layer is provided on a surface of the guide substrate. A first alignment guide is formed on the removable layer, and a second ...


5
H Bernhard Pogge, Subramania S Iyer: Process for precise multichip integration and product thereof. International Business Machines Corporation, Joseph P Abate Esq, Whitham Curtis & Whitham, May 23, 2000: US06066513 (51 worldwide citation)

Process for making an integrated circuit module and product thereof including a carrier supporting a plurality of precisely aligned semiconductor circuit chips having uniform thicknesses.


6
Toshiharu Furukawa, Mark C Hakey, Steven J Holmes, David V Horak, H Bernhard Pogge, Edmund J Sprogis, Steven H Voldman: Structure and process for multi-chip chip attach with reduced risk of electrostatic discharge damage. International Business Machines Corporation, Lawrence R Fraley Esq, Ratner & Prestia, August 6, 2002: US06429045 (48 worldwide citation)

A technique for fabricating precision aligned macros (PAMs) with reduced risk of electrostatic discharge damage and thermal damage. An electrical and thermal contact is provided through the back of the individual chips to a supporting silicon substrate. A conductive seed layer for electroplating is ...


7
H Bernhard Pogge, Chandrika Prasad, Roy Yu: Method of fabricating integrated electronic chip with an interconnect device. International Business Machines Corporation, Jay H Anderson, March 8, 2005: US06864165 (41 worldwide citation)

A method is described for forming an integrated structure, including a semiconductor device and connectors for connecting to a motherboard. A first layer is formed on a plate transparent to ablating radiation, and a second layer on the semiconductor device. The first layer has a first set of conduct ...


8
H Bernhard Pogge, Johann Greschner, Howard L Kalter: Very dense integrated circuit package. International Business Machines Corporation, Joseph P Abate Esq, Whitham Curtis & Whitham, September 29, 1998: US05814885 (26 worldwide citation)

An integrated circuit package including a carrier having a surface topography of projections or recesses for supporting individual semiconductor circuit chips having a conversely matching bottom surface topography to permit self-aligned positioning of the chip on the carrier.


9
H Bernhard Pogge, Chandrika Prasad, Roy Yu: Process for making fine pitch connections between devices and structure made by the process. International Business Machines Corporation, Jay H Anderson, September 3, 2002: US06444560 (25 worldwide citation)

A semiconductor device structure including fine-pitch connections between chips is fabricated using stud/via matching structures. A stud is provided on the front surface of the chip, and a layer with interconnection wiring is formed on a transparent plate. The wiring layer includes a conducting pad ...


10
H Bernhard Pogge, Michel Despont, Ute Drechsler, Peter Vettiger, Roy Yu: Three-dimensional integrated CMOS-MEMS device and process for making the same. International Business Machines Corporation, Ira D Blecker, July 4, 2006: US07071031 (23 worldwide citation)

A vertically integrated structure includes a micro-electromechanical system (MEMS) and a chip for delivering signals to the MEMS. The structure includes a metal stud connecting a surface of the chip and the MEMS; the MEMS has an anchor portion having a conducting pad on an underside thereof contacti ...