1
Guy Cohen: Method circuit and system for read error detection in a non-volatile memory array. Saifun Semiconductors, Eitan Law Group, January 31, 2006: US06992932 (309 worldwide citation)

The present invention is a method, circuit and system for determining a reference voltage to be used in reading cells programmed to a given program state. Some embodiments of the present invention relate to a system, method and circuit for establishing a set of operating reference cells to be used i ...


2
Guy Cohen: Method circuit and system for determining a reference voltage. Aifun Semiconductors, Eitan Law Group, November 8, 2005: US06963505 (117 worldwide citation)

The present invention is a method, circuit and system for determining a reference voltage. Some embodiments of the present invention relate to a system, method and circuit for establishing a set of operating reference cells to be used in operating (e.g. reading) cells in an NVM block or array. As pa ...


3
Guy Cohen, Michael A Guillorn, Alfred Grill, Leathen Shi: Accurate control of distance between suspended semiconductor nanowires and substrate surface. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Louis J Percello Esq, January 6, 2015: US08927968 (76 worldwide citation)

A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride l ...


4
Sarunya Bangsaruntip, Guy Cohen, Jeffrey W Sleight: Maskless process for suspending and thinning nanowires. International Business Machines Corporation, Vazken Alexanian, Michael J Chang, February 8, 2011: US07884004 (38 worldwide citation)

Semiconductor-based electronic devices and techniques for fabrication thereof are provided. In one aspect, a device is provided comprising a first pad; a second pad and a plurality of nanowires connecting the first pad and the second pad in a ladder-like configuration formed in a silicon-on-insulato ...


5
Guy Cohen, Boaz Eitan: Method, system and circuit for programming a non-volatile memory array. Saifun Semiconductor, Eitan Law Group, November 14, 2006: US07136304 (32 worldwide citation)

The present invention is a multi-phase method, circuit and system for programming non-volatile memory (“NVM”) cells in an NVM array. The present invention may include a controller to determine when, during a first programming phase, one or more NVM cells of a first set of cells reaches or exceeds to ...


6
Eduardo Maayan, Guy Cohen, Boaz Eitan: Method for reading non-volatile memory cells. Saifun Semiconductors, Eitan Law Group, August 14, 2007: US07257025 (30 worldwide citation)

A method includes changing a read reference level for reading a group of memory cells as a function of changes in a threshold voltage distribution of a different group of memory cells. The changing step includes determining a history read reference level for correct reading of at least one history c ...


7
Assaf Shappir, Eli Lusky, Guy Cohen: Method for reading non-volatile memory cells. Saifun Semiconductors, Eitan Law Group, July 10, 2007: US07242618 (26 worldwide citation)

A method includes changing a read reference level for reading a group of memory cells as a function of changes in a threshold voltage distribution of a different group of memory cells. The changing step includes determining a history read reference level of a group of history cells associated with a ...


8
Guy Cohen, Conal E Murray, Michael J Rooks: p-FET with a strained nanowire channel and embedded SiGe source and drain stressors. International Business Machines Corporation, Vazken Alexanian, Michael J Chang, March 19, 2013: US08399314 (23 worldwide citation)

Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET includes the following steps. A doped substrate having a dielectric thereon is provided. At least one s ...


9
Sarunya Bangsaruntip, Guy Cohen, Jeffrey W Sleight: Maskless process for suspending and thinning nanowires. International Business Machines Corporation, Vazken Alexanian, Michael J Chang, May 14, 2013: US08441043 (18 worldwide citation)

Semiconductor-based electronic devices and techniques for fabrication thereof are provided. In one aspect, a device is provided comprising a first pad; a second pad and a plurality of nanowires connecting the first pad and the second pad in a ladder-like configuration formed in a silicon-on-insulato ...


10
Guy Cohen, Michael A Guillorn, Conal Eugene Murray: Compressive (PFET) and tensile (NFET) channel strain in nanowire FETs fabricated with a replacement gate process. International Business Machines Corporation, Vazken Alexanian, Michael J Chang, July 23, 2013: US08492208 (18 worldwide citation)

A method of fabricating a FET device is provided which includes the following steps. Nanowires/pads are formed in a SOI layer over a BOX layer, wherein the nanowires are suspended over the BOX. A HSQ layer is deposited that surrounds the nanowires. A portion(s) of the HSQ layer that surround the nan ...