1
John T Orton, Cau L Nguyen, Gurbir Singh, Xia Dai, Raviprakash Nagaraj, Edwin J Pole II: Changing clock frequency. Intel Corporation, Trop Pruner & Hu P C, September 12, 2000: US06118306 (89 worldwide citation)

A system includes a component (e.g., a processor) that includes a clock generator that generates an internal clock running at a frequency. A controller generates a clock frequency change indication and places the component into a low activity state (e.g., deep sleep, stop grant, or other state). The ...


2
Nitin V Sarangdhar, Konrad K Lai, Gurbir Singh, Michael W Rhodehamel, Matthew A Fisch: Computer system with distributed bus arbitration scheme for symmetric and priority agents. Intel Corporation, Blakely Sokoloff Taylor & Zafman, December 3, 1996: US05581782 (66 worldwide citation)

A system and method for providing a high performance symmetric arbitration protocol that includes support for priority agents. The bus arbitration protocol supports two classes of bus agents: symmetric agents and priority agents. The symmetric agents support fair, distributed arbitration using a rou ...


3
Gurbir Singh, Robert J Greiner, Stephen S Pawlowski, David L Hill, Donald D Parker: Quad pumped bus architecture and protocol. Intel Corporation, Antonelli Terry Stout & Kraus, July 29, 2003: US06601121 (63 worldwide citation)

A bidirectional multidrop processor bus is connected to a plurality of bus agents. Bus throughput can be increased by operating the bus in a multi pumped signaling mode in which multiple information elements are driven onto a bus by a driving agent at a rate that is a multiple of the frequency of th ...


4
Wen Hann Wang, Konrad K Lai, Gurbir Singh, Mandar S Joshi, Nitin V Sarangdhar, Matthew A Fisch: Apparatus and method for caching lock conditions in a multi-processor system. Intel Corporation, Blakely Sokoloff Taylor & Zafman, December 21, 1999: US06006299 (50 worldwide citation)

In a computer system, an apparatus for handling lock conditions wherein a first instruction executed by a first processor processes data that is common to a second processor while the second processor is locked from simultaneously executing a second instruction that also processes this same data. A ...


5
Dan Patterson, Bindi Prasad, Gurbir Singh, Peter MacWilliams, Steve Hunt, Phil G Lee: Processor-cache protocol using simple commands to implement a range of cache configurations. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 13, 2001: US06202125 (42 worldwide citation)

A computer system having a processor-cache protocol supporting multiple cache configurations is described. The computer system has a processor having a cache control circuit to control multiple cache memory circuits. The processor including its cache control circuit is coupled to a cache bus. A seco ...


6
Phillip G Lee, Eileen Riggs, Gurbir Singh, Randy Steck: Microprocessor simultaneously issues an access to an external cache over an external cache bus and to an internal cache, cancels the external cache access on an internal cache hit, and reissues the access over a main memory bus on an external cache miss. Intel Corporation, Owen L Lamb, September 6, 1994: US05345576 (40 worldwide citation)

A data processing system which includes a microprocessor fabricated on an integrated circuit chip, a main memory external to the integrated circuit chip, and a backside cache external to the integrated circuit chip. The backside cache includes a directory RAM for storing cache address tag and encode ...


7
Nitin V Sarangdhar, Konrad K Lai, Gurbir Singh, Peter D MacWilliams, Stephen S Pawlowski, Michael W Rhodehamel: Method and apparatus for performing deferred transactions. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 25, 1997: US05615343 (39 worldwide citation)

A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents an ...


8
Ak Wing Leong, Gurbir Singh, Poh Huat Lye, Sai Mun Lee: Optical navigation sensor with integrated lens. Agilent Technologies, November 22, 2005: US06967321 (37 worldwide citation)

An optical navigation sensor apparatus for an optical mouse includes an optical navigation sensor having an electronic chip, an aperture plate and an imaging lens integrated into a single package. The imaging lens includes a lens housing surrounding the aperture and providing a barrier to the entry ...


9
Gurbir Singh, Michael W Rhodehamel: Method and apparatus for providing synchronous data transmission between digital devices operating at frequencies having a P/Q integer ratio. Intel Corporation, Blakely Sokoloff Taylor & Zafman, May 19, 1998: US05754833 (36 worldwide citation)

An apparatus for synchronously transmitting data between devices operating at different frequencies that have a P/Q integer ratio relationship. The apparatus allows one or more device(s) operating at a high frequency to synchronously exchange data with one or more device(s) operating at a low freque ...


10
Gurbir Singh, Wen Hann Wang, Michael W Rhodehamel, John M Bauer, Nitin V Sarangdhar: Method and apparatus for cache memory replacement line identification. Intel Corporation, Blakely Sokoloff Taylor & Zafman, September 15, 1998: US05809524 (33 worldwide citation)

A method and apparatus for cache memory replacement line identification have a cache interface which provides a communication interface between a cache memory and a controller for the cache memory. The interface includes an address bus, a data bus, and a status bus. The address bus transfers request ...