1
Eugene P Matter, Yahya S Sotoudeh, Gregory S Mathews: Method and apparatus for independently stopping and restarting functional units. Intel Corporation, Blakely Sokoloff Taylor & Zafman, February 21, 1995: US05392437 (210 worldwide citation)

A mechanism for powering down a functional unit on an integrated circuit having multiple functional units. Some of the functional units are clocked independently of each other. A method and mechanism for indicating to the functional unit whether it is required for use. Also included is a method and ...


2
Eugene P Matter, Yahya S Sotoudeh, Gregory S Mathews: Method and apparatus for independently stopping and restarting functional units. Intel Corporation, Blakely Sokoloff Taylor & Zafman, May 27, 1997: US05634131 (115 worldwide citation)

A mechanism and means for powering down a functional unit on an integrated circuit having multiple functional units. Some of the functional units are clocked independently of each other. The present invention includes a method and mechanism for indicating to the functional unit whether it is require ...


3
Gregory S Mathews, Edward S Zager: Cache memory hierarchy having a large write through first level that allocates for CPU read misses only and a small write back second level that allocates for CPU write misses only. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 25, 1994: US05359723 (40 worldwide citation)

A cache memory hierarchy having a first level write through cache memory and a second level write back cache memory is provided to a computer system having a CPU, a main memory, and a number of DMA devices. The first level write through cache memory responds to read and write accesses by the CPU, an ...


4
Ketan S Bhat, Gregory S Mathews: Multi-processing cache coherency protocol on a local bus. Intel Corporation, Blakely Sokoloff Taylor & Zafman, September 1, 1998: US05802577 (39 worldwide citation)

A computer system maintaining cache coherency among a plurality of caching devices coupled across a local bus includes a bus master, a memory, and a plurality of cache complexes, all coupled to the local bus. When the bus master requests a read or write with the memory, the cache complexes snoop the ...


5
Gregory S Mathews, Deepak J Aatresh, Sanjay Jain: Method and apparatus for reduced latency in hold bus cycles. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 14, 1995: US05398244 (30 worldwide citation)

An innovative protocol and system for implementing the same enables quick release of the bus by the master device, such as a CPU, to permit slave devices access to the bus. In one embodiment, the arbiter can select between the original hold protocol and quick hold protocol according to predetermined ...


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Gregory S Mathews: System and method for translation buffer accommodating multiple page sizes. Intel Corporation, Schwegman Lundberg Woessner & Kluth P A, September 23, 2003: US06625715 (23 worldwide citation)

A translation buffer is described which can translate virtual addresses to physical addresses wherein the virtual addresses have varying page sizes. The translation buffer includes a decoder to generate a hashed index, the index identifying an entry into two arrays. The first of the two arrays ident ...


8
Deepak J Aatresh, Tosaku Nakanishi, Gregory S Mathews: Central processing unit address pipelining. Intel Corporation, Blakely Sokoloff Taylor & Zafman, November 21, 1995: US05469544 (21 worldwide citation)

A microprocessor for use in a computer system which pipelines addresses for both burst and non-burst mode data transfers. By pipelining addresses, the microprocessor is able to increase the throughput of data transfers in the system. In the present invention, bits are used which may be programmed to ...


9
Gregory S Mathews, Edward T Grochowski, Chih Hung Chung: Apparatus and method for reducing power consumption due to cache and TLB accesses in a processor front-end. Intel Corporation, Blakely Sokoloff Taylor & Zafman, January 13, 2004: US06678815 (21 worldwide citation)

An apparatus and method for reducing power consumption in a processor front end are provided. The processor includes an instruction cache, a TLB, and a branch predictor. For sequential code execution, the instruction cache is disabled unless the next instruction fetch will cross a cache line boundar ...


10
John Wai Cheong Fu, Dean A Mulla, Gregory S Mathews, Stuart E Sailer: Dual-ported, pipelined, two level cache system. Intel Corporation, Schwegman Lundberg Woessner & Kluth P A, August 7, 2001: US06272597 (20 worldwide citation)

A novel on-chip cache memory and method of operation are provided which increase microprocessor performance. The on-chip cache memory has two levels. The first level is optimized for low latency and the second level is optimized for capacity. Both levels of cache are pipelined and can support simult ...