1
Gregory E Atwood, Albert Fazio, Richard A Lodenquai: Apparatus for providing block erasing in a flash EPROM. Intel Corporation, Blakely Sokoloff Taylor & Zafman, November 12, 1991: US05065364 (158 worldwide citation)

A flash EPROM memory array having vertical blocking is described. The array is organized into a plurality of vertical (column) blocks. Each block includes a source region switch which couples all the source regions in the memory cells in its respective block to a programming potential, ground or a d ...


2
Albert Fazio, Gregory E Atwood, James Q Mi: Method and circuitry for storing discrete amounts of charge in a single memory element. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 8, 1995: US05440505 (157 worldwide citation)

A method and circuitry for programming a memory cell to one of at least three amounts of charge. The amount of charge placed in the memory cell is increased by increasing the voltage level of a programming pulse applied to the memory cell.


3
Albert Fazio, Gregory E Atwood, Mark E Bauer: Method and apparatus for sensing the state of floating gate memory cells by applying a variable gate voltage. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 16, 1996: US05508958 (156 worldwide citation)

A method and apparatus for sensing the state of floating gate memory cells in a memory array. Because of its stability and accuracy, the sensing apparatus may be used for sensing the state of multi-bit floating gate memory cells. The state of a memory cell is sensed by applying a variable gate volta ...


4
Kerry D Tedrow, Stephen N Keeney, Albert Fazio, Gregory E Atwood, Johnny Javanifard, Kenneth Woiciechowski: High precision voltage regulation circuit for programming multilevel flash memory. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 5, 1996: US05497119 (141 worldwide citation)

A voltage regulation circuit that includes a sample and hold circuit for sampling an input voltage and for holding a reference voltage generated in response to the input voltage. The sample and hold circuit includes a capacitor that holds the reference voltage. The voltage regulation circuit also in ...


5
Neal Mielke, Gregory E Atwood, Amit Merchant: Method of repairing overerased cells in a flash memory. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 17, 1993: US05237535 (133 worldwide citation)

A method of repairing overerased cells in a flash memory array including a column having a first cell and a second cell is described. Repair begins by determining whether a first cell is overerased and applying a programming pulse if so. Next, the second cell is examined to determine whether it is o ...


6
Albert Fazio, Gregory E Atwood, James Q Mi: Method and circuitry for storing discrete amounts of charge in a single memory element. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 15, 1996: US05566125 (100 worldwide citation)

A method and circuitry for programming a memory cell to one of at least three amounts of charge. The amount of charge placed in the memory cell is increased by increasing the voltage level of a programming pulse applied to the memory cell.


7
Albert Fazio, Gregory E Atwood, James Q Mi: Method and circuitry for storing discrete amounts of charge in a single memory element. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 6, 1999: US05892710 (98 worldwide citation)

A method and circuitry for programming a memory cell to one of at least three amounts of charge. The amount of charge placed in the memory cell is increased by increasing the voltage level of a programming pulse applied to the memory cell.


8
Kerry D Tedrow, Stephen N Keeney, Albert Fazio, Gregory E Atwood, Johnny Javanifard, Kenneth Wojciechowski: High precision voltage regulation circuit for programming multiple bit flash memory. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 13, 1996: US05546042 (97 worldwide citation)

A voltage regulation circuit that includes a sample and hold circuit for sampling an input voltage and for holding a reference voltage generated in response to the input voltage. The sample and hold circuit includes a capacitor that holds the reference voltage. The voltage regulation circuit also in ...


9
Stephen N Keeney, Gregory E Atwood: Structure and method for low current programming of flash EEPROMS. Intel Corporation, Blakely Sokoloff Taylor & Zafman, January 23, 1996: US05487033 (92 worldwide citation)

A system and method for programming non-volatile memory enables fast low current programming. Low current programming is achieved by applying a source bias voltage and increasing the drain voltage to be greater than the source bias voltage to maintain fast programming. Furthermore, the control gate ...


10
Albert Fazio, Gregory E Atwood, Neal R Mielke: Floating gate non-volatile memory with blocks and memory refresh. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 24, 1993: US05239505 (92 worldwide citation)

A non-volatile memory device is described. The memory device includes a first block and a second block. The first block includes a first memory cell having a drain region, a source region, a floating gate, and a control gate. A first word line is coupled to the control gate of the first memory cell. ...