1
Graham R Wolstenholme, Philip J Ireland: Polysilicon pillar diode for use in a non-volatile memory cell. Micron Technology, Fletcher & Associates, May 12, 1998: US05751012 (484 worldwide citation)

There is described a memory cell having a vertically oriented polysilicon pillar diode for use in delivering large current flow through a variable resistance material memory element. The pillar diode comprises a plurality of polysilicon layers disposed in a vertical stack between a wordline and digi ...


2
Graham R Wolstenholme, Fernando Gonzalez, Russell C Zahorik: Memory cell incorporating a chalcogenide element and method of making same. Micron Technology, Fletcher Yoder & Van Someren, May 22, 2001: US06236059 (395 worldwide citation)

A memory cell incorporating a chalcogenide element and a method of making same is disclosed. In the method, a doped silicon substrate is provided with two or more polysilicon plugs to form an array of diode memory cells. A layer of silicon nitride is disposed over the plugs. Using a poly-spacer proc ...


3
Graham R Wolstenholme, Steven T Harshfield, Raymond A Turi, Fernando Gonzalez, Guy T Blalock, Donwon Park: Method of making small pores defined by a disposable internal spacer for use in chalcogenide memories. Micron Technology, Fletcher Yoder & Edwards, September 29, 1998: US05814527 (387 worldwide citation)

A method for fabricating an ultra-small pore or contact for use in chalcogenide memory cells specifically and in semiconductor devices generally in which disposable spacers are utilized to fabricate ultra-small pores or contacts. The pores thus defined have minimum lateral dimensions ranging from ap ...


4
Graham R Wolstenholme, Fernando Gonzalez, Russell C Zahorik: Memory cell incorporating a chalcogenide element and method of making same. Micron Technology, Fletcher Yoder & Edwards, December 7, 1999: US05998244 (298 worldwide citation)

A memory cell incorporating a chalcogenide element and a method of making same is disclosed. In the method, a doped silicon substrate is provided with two or more polysilicon plugs to form an array of diode memory cells. A layer of silicon nitride is disposed over the plugs. Using a poly-spacer proc ...


5
Fernando Gonzalez, Raymond A Turi, Graham R Wolstenholme, Charles L Ingalls: Three-dimensional container diode for use with multi-state material in a non-volatile memory cell. Micron Technology, Fletcher Yoder & Edwards, November 3, 1998: US05831276 (254 worldwide citation)

A vertically oriented diode for use in delivering current to a multi-state memory element in a memory cell. A vertical diode may be disposed in a diode container extending downwardly from a top of a silicon or oxide layer, and may be formed of a combination of silicon and/or metal layers disposed pr ...


6
Graham R Wolstenholme, Steven T Harshfield, Raymond A Turi, Fernando Gonzalez, Guy T Blalock, Donwon Park: Small pores defined by a disposable internal spacer for use in chalcogenide memories. Micron Technology, Fletcher Yoder & Van Someren, August 29, 2000: US06111264 (250 worldwide citation)

A method for fabricating an ultra-small pore or contact for use in chalcogenide memory cells specifically and in semiconductor devices generally in which disposable spacers are utilized to fabricate ultra-small pores or contacts. The pores thus defined have minimum lateral dimensions ranging from ap ...


7
Graham R Wolstenholme, Fernando Gonzalez, Russell C Zahorik: Method of making memory cell incorporating a chalcogenide element. Micron Technology, Fletcher Yoder & Van Someren, October 19, 1999: US05970336 (248 worldwide citation)

A memory cell incorporating a chalcogenide element and a method of making same is disclosed. In the method, a doped silicon substrate is provided with two or more polysilicon plugs to form an array of diode memory cells. A layer of silicon nitride is disposed over the plugs. Using a poly-spacer proc ...


8
Graham R Wolstenholme, Fernando Gonzalez, Russell C Zahorik: Memory cell incorporating a chalcogenide element. Micron Technology, Fletcher Yoder & Van Someren, November 28, 2000: US06153890 (225 worldwide citation)

A memory cell incorporating a chalcogenide element and a method of making same is disclosed. In the method, a doped silicon substrate is provided with two or more polysilicon plugs to form an array of diode memory cells. A layer of silicon nitride is disposed over the plugs. Using a poly-spacer proc ...


9
Fernando Gonzalez, Raymond A Turi, Graham R Wolstenholme, Charles L Ingalls: Fabrication of three dimensional container diode for use with multi-state material in a non-volatile memory cell. Micron Technology, Fletcher Yoder & Van Someren, November 16, 1999: US05985698 (216 worldwide citation)

A vertically oriented diode for use in delivering current to a multi-state memory element in a memory cell. A vertical diode may be disposed in a diode container extending downwardly from a top of a silicon or oxide layer, and may be formed of a combination of silicon and/or metal layers disposed pr ...


10
Graham R Wolstenholme, Albert Bergemont: Method of controlling oxide thinning in an EPROM or flash memory array. National Semiconductor Corporation, Limbach & Limbach, March 14, 1995: US05397725 (92 worldwide citation)

A method of fabricating an electrically-programmable read-only-memory (EPROM) or a flash memory array structure that controls oxide thinning to prevent shorts in the array and trenching of the bit lines is provided. The method includes the following steps. First, in accordance with conventional proc ...