1
Matthew D Pressly, Grady L Giles, Alfred L Crouch: Wrapper cell architecture for path delay testing of embedded core microprocessors and method of operation. Motorola, Keith E Witek, March 30, 1999: US05889788 (75 worldwide citation)

An integrated circuit contains customer specified logic (12), an embedded core (14), and a plurality of speed path test cells (16 and 18). Once the core (14) is embedded within an integrated circuit (10), not all of the input and output terminals of the embedded core are available at external termin ...


2
Grady L Giles, Alfred Larry Crouch, Odis Dale Amason Jr, Matthew Donald Pressly, Clark Gilson Shepard, Michael Alan Mateja, Lee Allen Corley, Daniel T Marquette, Jason E Doege: Scan based testing of an integrated circuit for compliance with timing specifications. Motorola, Daniel D Hill, September 22, 1998: US05812561 (67 worldwide citation)

A method and implementation for providing an improved testable design for an integrated circuit (IC) device. The integrated circuit includes a functional path for the implementation of a functional specification as well as a testing path for testing the timing specifications for the integrated circu ...


3
Grady L Giles, Jesse R Wilson: Toggle-free scan flip-flop. Motorola, Charlotte B Whitaker, May 14, 1991: US05015875 (43 worldwide citation)

A toggle-free scan flip-flop (TFSFF) is provided which is designed for use during a test mode scan operation. The toggle-free scan flip-flop has the capability of not toggling its parallel output during test mode scan operation. The TFSFF uses a master latch, which is controlled by a scan multiplexo ...


4
Grady L Giles, Jesse R Wilson, Terry V Hulett: Accelerated test apparatus and support logic for a content addressable memory. Motorola, John A Fisher, Jeffrey Van Myers, David L Mossman, July 14, 1987: US04680760 (23 worldwide citation)

Accelerated test circuitry and support logic to test a content addressable memory (CAM). In a CAM array of n entries of m bits per entry, the testing of each word lind, each memory element, each exclusive OR (XOR) comparator and each match line may be thoroughly and quickly tested by means of the pa ...


5
Matthew D Pressly, Grady L Giles: Timing apparatus and timing method for wrapper cell speed path testing of embedded cores within an integrated circuit. Motorola, Keith E Witek, June 30, 1998: US05774476 (19 worldwide citation)

Wrapper cells (16 and 18) are coupled to inputs and outputs of an embedded core (14) within an integrated circuit (10). The wrapper cells (16 and 18) are used to test timing specifications of the embedded core after the embedded core has been integrated on-chip with other peripheral logic (12). In o ...


6
Grady L Giles, Yui K Ho, Robert B Cohen: Method and apparatus for indicating a duplication of entries in a content addressable storage device. Motorola, Elizabeth A Apperley, June 15, 1993: US05220526 (8 worldwide citation)

An apparatus (10) indicates a duplication of information stored in a content addressable memory (CAM 12) system at the time the information is written to the system. In the CAM system, Match line signals (Match 0-Match (N-1) are asserted when information being written to a predetermined row is ident ...


7
Joel T Irby, Grady L Giles, Alexander W Schaefer, Gregory A Constant, Floyd L Dankert, Amy M Novak: Apparatus for testing embedded memory read paths. Advanced Micro Devices, Meyertons Hood Kivlin Kowert & Goetzel P C, Erik A Heter, April 12, 2011: US07925937 (3 worldwide citation)

An integrated circuit. The integrated circuit includes a plurality of logic circuits. The integrated circuit further includes a scan chain including a plurality of scan elements coupled in series, wherein the scan chain is configured to load stimulus data to be applied to the logic circuits for test ...


8
Grady L Giles, William D Atwell Jr, Jesse R Wilson, Richard B Reis: Method and apparatus for shifting data in an array of storage elements in a data processing system. Motorola, Susan C Hill, November 29, 1994: US05369752 (1 worldwide citation)

A method and apparatus for shifting data in an array of storage elements (22-37) in a data processing system (10). In one form, the present invention uses multiplexer (MUX) logic (38) and Shift Control signals to selectively couple storage elements (22-37) to latches (39-42). In this manner, data va ...


9
Grady L Giles, James A Wingfield, Atchyuth K Gorti: Test circuit having scan warm-up. Advanced Micro Devices, Polansky & Associates P L L C, Paul J Polansky, June 2, 2015: US09046574 (1 worldwide citation)

A test circuit for a functional circuit includes a scan chain coupled to the functional circuit, and a controller coupled to the scan chain, for controlling the scan chain to scan a test pattern into the scan chain, and subsequently and repetitively for a multiple number of times launch the test pat ...


10
Grady L Giles, Brian Hoang, Timothy J Wood: Test access mechanism for multi-core processor or other integrated circuit. GLOBALFOUNDRIES, Meyertons Hood Kivlin Kowert & Goetzel P C, Erik A Heter, January 24, 2012: US08103924

A processor having a pipelined test access mechanism (TAM). The processor includes a plurality of processor cores. Each of the processor cores includes a scan chain including plurality of serially-coupled scan elements. The processor further includes the pipelined TAM, which includes a plurality of ...