1
Brandenburg Lane Howard, Gopinath Bhaskarpillai, Kurshan Robert Paul: Interconnected loop digital transmission system. Bell Telephone Laboratories Incorporated, June 26, 1973: US3742144 (16 worldwide citation)

A digital communication loop system wherein transfers of signal message blocks between interconnecting loops are only made when a Hamming distance criterion is satisfied. Appended to each message block is a loop destination address code comprised of a first ordered concatenation of two binary sequen ...


2
Kurshan Robert P, Gopinath Bhaskarpillai: Generateur de signaux a sequences periodiques utilisant larithmetique ordinaire, Periodic sequence generators using ordinary arithmetic. Western Electric Company Incorporated, December 11, 1979: CA1067968

PERIODIC SEQUENCE GENERATORS USING ORDINARY ARITHMETIC Abstract of the Disclosure Dislcosed are signal generators for developingmultilevel output signal sequences of a preselected periodof repetition. In their general form, the generatorscomprise a shift register capable of storing multilevelsignals ...


3
Gopinath Bhaskarpillai, Flores Christopher, Limb John O: Systeme et protocole pour eviter les collisions pour systeme de communications numerique a acces multiples a deux voies, Collision avoiding system and protocol for a two path multiple access digital communications system. Western Electric Company Incorporated, KIRBY EADES GALE BAKER, September 17, 1985: CA1193692

-25- COLLISION AVOIDING SYSTEM AND PROTOCOLFOR A TWO PATH MULTIPLE ACCESS DIGITAL COMMUNICATIONS SYSTEMAbstract In order to control the transfer of packets ofinformation among a plurality of stations, e.g., digitalcomputers, the instant communications system and protocolcontemplate first and second ...


4
Cohen David M, Gopinath Bhaskarpillai, Vollaro John R: Recepteur selectif pour processeur de systeme a processeurs multiples, Selective receiver for each processor in a multiple processor system. Cohen David M, Gopinath Bhaskarpillai, Vollaro John R, Bell Communications Research, CASSAN MACLEAN, October 27, 1992: CA1309503

Abstract of the Disclosure Circuitry, and associated methodology, in aparallel processing system (50) for sharing the addressspace among a plurality of autonomous processors(110,210,310) communicating over a common bus provides anefficient, non-destructive data transfer and storageenvironment. This ...


5
Gopinath Bhaskarpillai, Kurshan Robert P: Circuit oscillateur-detecteur recurrent, Recursive detector-oscillator circuit. Western Electric Company Incorporated, September 25, 1979: CA1063186

A RECURSIVE DETECTOR-OSCILLATOR CIRCUIT Abstract of the Disclosure Disclosed is a recursive circuit capable of servingas a signal detector or as a signal generator. The circuitcomprises a shift register capable of storing multilevelsignals, and a feedback network responsive to an inputsignal and to ...


6
Cohen David Mordecai, Gopinath Bhaskarpillai, Vollaro John Richard: Selective receiver for each processor in a multiple processor system. Bell Communications Research, WINTER Richard C, April 20, 1989: WO/1989/003565

Circuitry, and associated methodology, in a parallel processing system (50) for sharing the address space among a plurality of autonomous processors (110, 210, 310) communicating over a common bus provides an efficient, non-destructive data transfer and storage environment. This is effected by augme ...


7
Gopinath Bhaskarpillai, Kurshan David: Directly programmable networks. Network Programs, MICHAELSON Peter L, September 3, 1998: WO/1998/038768

A procedure for establishing a scalable spanning tree over a network composed of nodes and links in which the resources for each node are independent of the size of the network. The procedure involves the selection of a set of states, a set of messages, state transition rules as well as a completion ...


8
Gopinath Bhaskarpillai, Kurshan David: Composition of systems of objects by interlocking coordination, protection, and distribution. Networks Programs, MICHAELSON Peter L, December 23, 1998: WO/1998/058312

A methodology for developing scalable systems based on a technique for the composition of objects to form a larger, composite object using Interface Cycles, which are canonical programs, hardware, or abstractions which interlock protection, distribution, and coordination of data and control from the ...


9
Cohen David Mordecai, Gopinath Bhaskarpillai, Vollaro John Richard: Selective receiver for each processor in a multiple processor system.. Bell Communications Res, August 8, 1990: EP0380481-A1

Circuitry, and associated methodology, in a parallel processing system (50) for sharing the address space among a plurality of autonomous processors (110, 210, 310) communicating over a common bus provides an efficient, non-destructive data transfer and storage environment. This is effected by augme ...