1
Glenn J Hinton, David B Papworth, Andrew F Glew, Michael A Fetterman, Robert P Colwell: Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer. Intel Corporation, Blakely Sokoloff Taylor & Zafman, February 24, 1998: US05721855 (179 worldwide citation)

A pipelined method for executing instructions in a computer system. The present invention includes providing multiple instructions as a continuous stream of operations. This stream of operations is provided in program order. In one embodiment, the stream of operations is provided by performing an in ...


2
James M Brayton, Michael W Rhodehamel, Nitin V Sarangdhar, Glenn J Hinton: Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 22, 1997: US05623628 (137 worldwide citation)

A computer system, and a method performed by it, having a mechanism for ensuring consistency of data among various level(s) of caching in a multi-level hierarchical memory system. The cache consistency mechanism includes an external bus request queue which and associated mechanism, which cooperate t ...


3
Bradley D Hoyt, Glenn J Hinton, David B Papworth, Ashwani K Gupta, Michael A Fetterman, Subramanian Natarajan, Sunil Shenoy, Reynold V D Sa: Method and apparatus for resolving return from subroutine instructions in a computer processor. Intel Corporation, Blakely Sokoloff Taylor & Zafman, February 18, 1997: US05604877 (91 worldwide citation)

A method and apparatus for resolving Return From Subroutine instructions in a computer processor are disclosed. The method and apparatus resolve Return From Subroutine instructions in four stages. A first stage predicts Call Subroutine instructions and Return From Subroutine instructions within the ...


4
Andrew F Glew, Glenn J Hinton: Method and apparatus for processing memory-type information within a microprocessor. Intel Corporation, Blakely Sokoloff Taylor & Zafman, May 12, 1998: US05751996 (72 worldwide citation)

A memory-type value identifying the type of memory contained with a range of memory locations is explicitly stored within a microprocessor. Prior to processing a memory micro-instruction such as a load or store, the memory-type is determined for the memory location identified by the memory micro-ins ...


5
Bradley D Hoyt, Glenn J Hinton, David B Papworth, Ashwani K Gupta, Michael A Fetterman, Subramanian Natarajan, Sunil Shenoy, Reynold V D Sa: Method and apparatus for implementing a set-associative branch target buffer. Intel Corporation, Blakely Sokoloff Taylor & Zafman, November 12, 1996: US05574871 (69 worldwide citation)

A Branch Target Buffer Circuit in a computer processor that predicts branch instructions with a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache that stores branch information about previously executed branch instructions. The branch in ...


6
Robert F Krick, Glenn J Hinton, Michael D Upton, David J Sager, Chan W Lee: Trace based instruction caching. Intel Corporation, Blakely Sokoloff Taylor & Zafman, January 25, 2000: US06018786 (68 worldwide citation)

A cache memory is constituted with a data array and control logic. The data array includes a number of data lines, and the control logic operates to store a number of trace segments of instructions in the data lines, including trace segments that span multiple data lines. In one embodiment, each tra ...


7
Glenn J Hinton, Robert W Martell, Michael A Fetterman, David B Papworth, James L Schwartz: Circuit and method for scheduling instructions by predicting future availability of resources required for execution. Intel Corporation, Blakely Sokoloff Taylor & Zafman, September 10, 1996: US05555432 (67 worldwide citation)

An out-of-order execution processor comprising an execution unit, a storage unit and a scheduler is disclosed. The storage unit stores instructions awaiting availability of resources required for execution. The scheduler periodically determines whether resources required for executing each instructi ...


8
Jeffrey M Abramson, David B Papworth, Haitham H Akkary, Andrew F Glew, Glenn J Hinton, Kris G Konigsfeld, Paul D Madland: Out-of-order processor with a memory subsystem which handles speculatively dispatched load operations. May 12, 1998: US05751983 (64 worldwide citation)

A method and apparatus for speculatively dispatching and/or executing LOADs in a computer system includes a memory subsystem of a out-of-order processor that handles LOAD and STORE operations by dispatching them to respective LOAD and STORE buffers in the memory subsystem. When a LOAD is subsequentl ...


9
Haitham Akkary, Mandar S Joshi, Rob Murray, Brent E Lince, Paul D Madland, Andrew F Glew, Glenn J Hinton: Method and apparatus for implementing a single clock cycle line replacement in a data cache unit. Intel Corporation, Blakely Sokoloff Taylor & Zafman, June 11, 1996: US05526510 (64 worldwide citation)

The data cache unit includes a separate fill buffer and a separate write-back buffer. The fill buffer stores one or more cache lines for transference into data cache banks of the data cache unit. The write-back buffer stores a single cache line evicted from the data cache banks prior to write-back t ...


10
Jeffery M Abramson, Haitham Akkary, Andrew F Glew, Glenn J Hinton, Kris G Konigsfeld, Paul D Madland: Method and apparatus for blocking execution of and storing load operations during their execution. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 9, 1999: US05881262 (61 worldwide citation)

A method and apparatus for performing load operations in a computer system. The present invention includes a method and apparatus for dispatching the load operation to be executed. The present invention halts the execution of the load operation when a dependency exists between the load operation and ...