1
Harlan R Isaak, Andrew C Ross, Glen E Roeters: Panel stacking of BGA devices to form three-dimensional modules. Staktek Group, Andrews Kurth L, April 12, 2005: US06878571 (98 worldwide citation)

A chip stack comprising at least one base layer including a base substrate having a first conductive pattern disposed thereon. The chip stack further comprises at least one interconnect frame having a second conductive pattern disposed thereon which is electrically connected to the first conductive ...


2
Harlan R Isaak, Andrew C Ross, Glen E Roeters: Panel stacking of BGA devices to form three-dimensional modules. DPAC Technologies, Stetina Brunda Garred & Brucker, May 20, 2003: US06566746 (50 worldwide citation)

A chip stack comprising at least one base layer including a base substrate having a first conductive pattern disposed thereon. The chip stack further comprises at least one interconnect frame having a second conductive pattern disposed thereon which is electrically connected to the first conductive ...


3
Glen E Roeters, Andrew C Ross: CSP chip stack with flex circuit. Staktek Group, Andrews Kurth, July 25, 2006: US07081373 (29 worldwide citation)

A chip stack comprising a flex circuit including a flex substrate having a first conductive pattern disposed thereon and a plurality of leads extending therefrom. Also included in the chip stack are at least two integrated circuit chip packages. The integrated circuit chip packages may be electrical ...


4
Glen E Roeters, Frank E Mantz: Retaining ring interconnect used for 3-D stacking. DPAC Technologies, Stetina Brunda Garred & Brucker, June 3, 2003: US06573461 (24 worldwide citation)

A retaining ring interconnect. A retaining ring is formed on a perimeter of a pad on each of two adjoining surfaces of two PCB substrates. A conductive paste is applied between the pads on the two adjoining surfaces. The retaining rings are aligned and facing with each other. By performing a heat co ...


5
Glen E Roeters, Andrew C Ross: Stacking system and method. Stuktek Group, J Scott Denko, Fish & Richardson P C, March 20, 2007: US07193310 (10 worldwide citation)

A chip stack comprising a flex circuit including a flex substrate having a first conductive pattern disposed thereon and a plurality of leads extending therefrom. Also included in the chip stack are at least two integrated circuit chip packages. The integrated circuit chip packages may be electrical ...


6
Glen E Roeters, Frank E Mantz: Post in ring interconnect using for 3-D stacking. DPAC Technologies, Stetina Brunda Garred & Brucker, June 3, 2003: US06573460 (6 worldwide citation)

A post in ring interconnect used for 3-D stacking. A retaining ring is formed on a pad on a bottom surface of a top PCB substrate to be stacked with a bottom PCB substrate. A post is formed on a pad on a top surface of the bottom PCB substrate. A conductive paste is applied on the pad on the bottom ...


7
Glen E Roeters, John Patrick Sprint, Joel Andrew Mearig: Thin scale outline package. Staktek Group, Andrews Kurth, February 15, 2005: US06856010 (3 worldwide citation)

The present invention provides a plurality of vertically stacked semiconductor dies which are electrically connected to each other. Each semiconductor die has leads which extend out from at least two opposed side surfaces of the semiconductor die. Each lead defines a first junction, a second junctio ...


8
Glen E Roeters, John Patrick Sprint, Joel Andrew Mearig: Thin scale outline package stack. Kit M Stetina, Stetina Brunda Garred & Brucker, June 10, 2004: US20040108583-A1

A semiconductor die stack is provided which includes at least two semiconductor dies each having electrical leads. The leads of the upper semiconductor die are directly electrically connected to respective leads of the lower semiconductor die. Electrical connectivity is maintained throughout the sem ...


9
Glen E Roeters, John Patrick Sprint, Joel Andrew Mearig: Thin scale outline package. Kit M Stetina, Stetina Brunda Garred & Brucker, June 10, 2004: US20040108584-A1

The present invention provides a plurality of vertically stacked semiconductor dies which are electrically connected to each other. Each semiconductor die has leads which extend out from at least two opposed side surfaces of the semiconductor die. Each lead defines a first junction, a second junctio ...


10
Mike Grobler, Glen E Roeters, Rod Corder, Mike Zachan: Wireless connectivity module. Kit M Stetina Esq, Stetina Brunda Garred & Brucker, March 3, 2005: US20050048997-A1

A module is provided for imparting wireless functionality to a host device. Software running on an application processor of the module can facilitate data exchange between the host device and a wireless radio of the module by converting data between a host-oriented protocol and a wireless protocol, ...