1
Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J Adiletta: Mapping requests from a processing unit that uses memory-mapped input-output space. Intel Corporation, Fish & Richardson P C, February 17, 2004: US06694380 (147 worldwide citation)

A processor is disclosed that can map a request from a central processing unit that uses memory-mapped input-output space to a second processing domain, such as a multithreaded processing domain. A request addressed to the input-output space of the central processing unit is converted to a correspon ...


2
Matthew J Adiletta, Gilbert Wolrich, William Wheeler: Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode. Intel Corporation, Fish & Richardson P C, August 12, 2003: US06606704 (134 worldwide citation)

A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory con ...


3
Gilbert Wolrich, Debra Bernstein, Donald Hooper, Matthew J Adiletta, William Wheeler: Thread signaling in multi-threaded network processor. Intel Corporation, Fish & Richardson P C, September 23, 2003: US06625654 (120 worldwide citation)

A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple program threads. The processor also includes a memory control system that has a first memory cont ...


4
Debra Bernstein, Donald F Hooper, Matthew J Adiletta, Gilbert Wolrich, William Wheeler: Microengine for parallel processor architecture. Intel Corporation, Fish & Richardson P C, December 23, 2003: US06668317 (112 worldwide citation)

A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory con ...


5
Matthew J Adiletta, William Wheeler, James Redfield, Daniel Cutter, Gilbert Wolrich: SRAM controller for parallel processor architecture including address and command queue and arbiter. Intel Corporation, Fish & Richardson P C, July 30, 2002: US06427196 (106 worldwide citation)

A controller for a random access memory includes an address and command queue that holds memory references from a plurality of micro control functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue ...


6
Gilbert Wolrich, Debra Bernstein, Matthew J Adiletta, Donald F Hooper: Method and apparatus for gigabit packet assignment for multithreaded packet processing. Intel Corporation, Fish & Richardson P C, December 9, 2003: US06661794 (93 worldwide citation)

A network processor that has multiple processing elements, each processing element supporting multiple simultaneous program threads with access to shared resources in an interface. Packet data is received from high-speed ports in segments and each segment is assigned to one of the program threads. E ...


7
Gilbert Wolrich, Debra Bernstein, Matthew J Adiletta, William Wheeler: Arbitrating command requests in a parallel multi-threaded processing system. Intel Corporation, Fish & Richardson P C, March 11, 2003: US06532509 (88 worldwide citation)

A parallel, multi-threaded processor system and technique for arbitrating command requests is described. The system includes a plurality of microengines, a plurality of shared system resources and a global command arbiter. The global command arbiter uses a command request protocol that is based on t ...


8
Matthew J Adiletta, William Wheeler, James Redfield, Daniel Cutter, Gilbert Wolrich: SRAM controller for parallel processor architecture and method for controlling access to a RAM using read and read/write queues. Intel Corporation, Fish & Richardson P C, April 27, 2004: US06728845 (80 worldwide citation)

A controller for a random access memory (RAM), such as a static ram (SRAM), includes an address and command queue that holds memory references from a plurality of microcontrol functional units. The address and command queue includes a read queue that stores read memory references. The controller als ...


9
Gilbert Wolrich, Debra Bernstein, Matthew J Adiletta, William Wheeler: Handling contiguous memory references in a multi-queue system. Intel Corporation, Fish & Richardson P C, May 6, 2003: US06560667 (74 worldwide citation)

A controller for a random access memory has control logic, including an arbiter that detects a status of outstanding memory references. The controller selects a memory reference from one of a plurality queues of memory references. The control logic is responsive to a memory reference chaining bit th ...


10
Mark B Rosenbluth, Gilbert Wolrich, Debra Bernstein: Software controlled content addressable memory in a general purpose execution datapath. Intel Corporation, Fish & Richardson P C, March 15, 2005: US06868476 (73 worldwide citation)

A lookup mechanism provides an input value to a datapath element disposed in an execution datapath of a processor and causes the datapath element to compare the input value to stored identifier values. The lookup mechanism receives from the datapath element a result based on the comparison.