1
James P Ellis, Era Nangia, Nital Patwa, Bhavin Shah, Gilbert M Wolrich: Digital computer system with cache controller coordinating both vector and scalar operations. Digital Equipment Corporation, Denis G Maloney, Albert P Cefalo, May 23, 1995: US05418973 (72 worldwide citation)

A digital computer system includes a scalar CPU, a vector processor, and a shared cache memory. The scalar CPU has an execution unit, a memory management unit, and a cache controller unit. The execution unit generates load/store memory addresses for vector load/store instructions. The load/store add ...


2
James R Lundberg, Gilbert M Wolrich: State machine phase lock loop. Digital Equipment Corporation, Krishnendu Gupta, Ronald C Hudgens, Arthur W Fisher, September 22, 1998: US05811998 (62 worldwide citation)

A digital phase lock loop synchronizes a first signal to a second signal having a predefined frequency. The first signal usually has an instantaneous frequency greater than the predefined frequency, so that the first signal is constantly gaining phase with respect to the second signal. The digital p ...


3
Donald F Hooper, Matthew J Adiletta, Gilbert M Wolrich: Multi-threaded sequenced receive for fast network port stream of packets. Intel Corporation, Robert A Greenberg, October 4, 2005: US06952824 (48 worldwide citation)

A method of processing network data in a network processor includes using three or more threads to process a beginning portion, a middle portion, and an end portion of data packet. The first thread processes the beginning portion; one or more middle threads process the middle portion, and a last thr ...


4
Donald F Hooper, Matthew J Adiletta, Gilbert M Wolrich: Multi-threaded sequenced receive for fast network port stream of packets. Intel Corporation, Fish & Richardson P C, October 7, 2008: US07434221 (25 worldwide citation)

A method of processing network data in a network processor includes using three or more threads to process a beginning portion, a middle portion, and an end portion of data packet is presented. The first thread processes the beginning portion; one or more middle threads process the middle portion, a ...


5
Vinodh Gopal, Gilbert M Wolrich, Erdinc Ozturk, James D Guilford, Kirk S Yap, Sean M Gulley, Wajdi K Feghali, Martin G Dixon: SIMD integer multiply-accumulate instruction for multi-precision arithmetic. Intel Corporation, Nicholson De Vos Webster & Elliot, January 12, 2016: US09235414 (25 worldwide citation)

A multiply-and-accumulate (MAC) instruction allows efficient execution of unsigned integer multiplications. The MAC instruction indicates a first vector register as a first operand, a second vector register as a second operand, and a third vector register as a destination. The first vector register ...


6
Gilbert M Wolrich, Timothy C Fischer, John A Kowaleski Jr: Rounding adder for floating point processor. Digital Equipment Corporation, Diane C Drozenski, Ronald C Hudgens, Arthur W Fisher, December 2, 1997: US05694350 (23 worldwide citation)

A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding ...


7
Gilbert M Wolrich, Timothy C Fischer, John A Kowaleski Jr: Floating point unit data path alignment. Digital Equipment Corporation, Denis G Maloney, Arthur W Fisher, May 6, 1997: US05627773 (23 worldwide citation)

A pipelined floating point processor including an add pipe for performing floating point additions described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding ad ...


8
Gilbert M Wolrich, John A Kowaleski Jr: Multiply pipe round adder. Digital Equipment Corporation, Diane C Drozenski, Ronald C Hudgens, Arthur W Fisher, March 10, 1998: US05726927 (22 worldwide citation)

A multiplier in a floating point processor includes a circuit to determine for each bit of the multiplier operand a 3 times booth recode and a booth recode multiplier array which implements a 3 times booth recode multiplication. The multiplier includes logic to determine a fast sign extend to replac ...


9
William R Wheeler, Matthew James Adiletta, Samuel Ho, Debra Bernstein, Gilbert M Wolrich: Mechanism for high bandwidth DMA transfers in a PCI environment. Digital Equipment Corporation, Hamilton Brook Smith & Reynolds, October 19, 1999: US05968153 (19 worldwide citation)

A method and apparatus for maximizing the performance of DMA transfers over a PCI.TM. bus are provided which includes a Per-Channel Retry count, Double Buffer Management, Wait Enable functionality, Back Up register functionality, Gather/Scatter mapping, a method for minimization of PIO writes, Read ...


10
William R Wheeler, Matthew James Adiletta, Samuel Ho, Debra Bernstein, Gilbert M Wolrich: Mechanism for high bandwidth DMA transfers in a PCI environment. Digital Equipment Corporation, March 16, 1999: US05884050 (16 worldwide citation)

A method and apparatus for maximizing the performance of DMA transfers over a PCI.TM. bus are provided which includes a Per-Channel Retry count, Double Buffer Management, Wait Enable functionality, Back Up register functionality, Gather/Scatter mapping, a method for minimization of PIO writes, Read ...