1
Gigy Baror, Brian W Case, Rod G Fleck, Philip M Freidin, Smeeta Gupta, William M Johnson, Cheng Gang Kong, Ole H Moller, Timothy A Olson, David I Sorensen: Streamlined instruction processor. Advanced Micro Devices, Fliesler Dubb Meyer & Lovejoy, May 15, 1990: US04926323 (137 worldwide citation)

A streamlined instruction processor processes data in response to a program composed of prespecified instructions in pipeline cycles. The processor comprises an instruction fetch unit, including an instruction interface adapted for connection to an instruction memory and for fetching instructions fr ...


2
Gigy Baror: Organization of an integrated cache unit for flexible usage in cache system design. Advanced Micro Devices, Lowe Price LeBlanc Becker & Shur, June 18, 1991: US05025366 (131 worldwide citation)

Methods and apparatus are disclosed for realizing an integrated cache unit which may be flexibly used for cache system design. The preferred embodiment of the invention comprises both a cache memory and a cache controller on a single chip. In accordance with an alternative embodiment of the inventio ...


3
Gigy Baror, William M Johnson: Programmable cache memory as well as system incorporating same and method of operating programmable cache memory. Advanced Micro Device, Lowe Price LeBlanc & Becker, February 9, 1993: US05185878 (78 worldwide citation)

Methods and apparatus are disclosed for realizing an integrated cache unit (ICU) comprising both a cache memory and a cache controller on a single chip. The novel ICU is capable of being programmed, supports high speed data and instruction processing applications in both Reduced Instruction Set Comp ...


4
William M Johnson, Gigy Baror: High performance processor interface between a single chip processor and off chip memory means having a dedicated and shared bus structure. Advanced Micro Devices, Joseph J Kaliko, J Vincent Tortulano, July 25, 1989: US04851990 (76 worldwide citation)

Methods and apparatus for realizing a high performance interface between a processor, constituting part of a reduced instruction set computer (RISC) system, and a set of devices, including memory means. According to the invention, the interface includes three independent buses. A shared processor ou ...


5
Gigy Baror: Organization of an integrated cache unit for flexible usage in supporting microprocessor operations. Advanced Micro Devices, B Noel Kivlin, Conley Rose & Tayon P C, May 6, 1997: US05627992 (65 worldwide citation)

A computer system having a cache memory subsystem which allows flexible setting of caching policies on a page basis and a line basis. A cache block status field is provided for each cache block to indicate the cache block's state, such as shared or exclusive. The cache block status field controls wh ...


6
Gigy Baror: Methods and apparatus for caching interlock variables in an integrated cache memory. Advanced Micro Devices, Lowe Price LeBlanc & Becker, August 4, 1992: US05136691 (42 worldwide citation)

Methods and apparatus are disclosed for supporting the caching of interlock variables in cache memory units employed in multiprocessor and/or multitasking environments. The preferred embodiment of the invention includes methods and apparatus for selectively treating interlock variables as cachable o ...


7
Gigy Baror: Organization of an integrated cache unit for flexible usage in supporting multiprocessor operations. Advanced Micro Devices, B Noel Kivlin, Conley Rose & Tayon PC, January 11, 2000: US06014728 (40 worldwide citation)

A computer system having a cache memory subsystem which allows flexible setting of caching policies on a page basis and a line basis. A cache block status field is provided for each cache block to indicate the cache block's state, such as shared or exclusive. The cache block status field controls wh ...


8
Rod G Fleck, Ole H Moller, Gigy Baror: Execution of a loop instructing in a loop pipeline after detection of a first occurrence of the loop instruction in an integer pipeline. Siemens Aktiengesellschaft, June 13, 2000: US06076159 (39 worldwide citation)

A data processor is disclosed which comprises a first pipeline for decoding and executing data instructions, a second pipeline for decoding and executing address instructions, a unit for issuing multiple instructions to the pipelines, a first set of registers being coupled with the first pipeline, a ...


9
Rod G Fleck, Klaus Oberlaender, Gigy Baror, Alfred Eder, Le Trong Nguyen: Data processing device with memory coupling unit. Infineon Technologies North America, Fish & Richardson P C, June 11, 2002: US06405273 (37 worldwide citation)

A data processing unit is disclosed with a register file having a plurality of registers. A memory having a plurality of n-bit input/output ports, and a coupling unit for coupling the memory with the register file, a memory address and select unit for addressing the memory banks are provided. The co ...


10
Klaus Oberlaender, Sabeen Randhawa, Yannick Martelloni, Manfred Henftling, Rami Zemach, Zohar Peleg, Christian Wiedholz, Gigy Baror, Doron Shoham, Oded Trainin, Niv Margalit: Interface for a memory unit. Infineon Technologies North American, Fish & Richardson P C, January 14, 2003: US06507899 (31 worldwide citation)

An interface circuit for coupling a data handling unit with a memory unit having control inputs, an address signal input, a data signal input, and a data signal output is described. The interface circuit comprises an address buffer having an input and an output, said input receiving an address signa ...