Bijan Davari, Devendra Kumar Sadana, Ghavam G Shahidi, Sandip Tiwari: Patterned SOI regions in semiconductor chips. International Business Machines Corporation, Robert M Trepp, December 25, 2001: US06333532 (159 worldwide citation)

A method and structure for forming patterned SOI regions and bulk regions is described wherein a silicon containing layer over an insulator may have a plurality of selected thickness' and wherein bulk regions may be suitable to form DRAM's and SOI regions may be suitable to form merged log ...

Fariborz Assaderaghi, Bijan Davari, Louis L Hsu, Jack A Mandelman, Ghavam G Shahidi: Two-device memory cell on SOI for merged logic and memory applications. International Business Machines Corporation, Joseph P Abate, Whitham Curtis & Whitham, July 21, 1998: US05784311 (155 worldwide citation)

A two-MOSFET device memory cell, based on conventional SOI complementary metal oxide technology, in which charge is stored on the body of a first MOSFET, with a second MOSFET connected to the body for controlling the charge in accordance with an information bit. Depending on the stored charge, the b ...

Effendi Leobandung, Devendra K Sadana, Dominic J Schepis, Ghavam G Shahidi: Process of making densely patterned silicon-on-insulator (SOI) region on a wafer. International Business Machines Corporation, Joseph P Abate Esq, Ratner & Prestia, April 10, 2001: US06214694 (133 worldwide citation)

A process for making a SOI region and a bulk region in a semiconductor device. The process includes providing a SOI structure. The SOI structure has a thin silicon layer, a buried insulating oxide layer underlying the thin silicon layer, and a silicon substrate underlying the buried insulating oxide ...

Diane C Boyd, Judson R Holt, MeiKei Ieong, Renee T Mo, Zhibin Ren, Ghavam G Shahidi: Ultra-thin body super-steep retrograde well (SSRW) FET devices. International Business Machines Corporation, Graham S Jones II, H Daniel Schnurmann, February 21, 2006: US07002214 (118 worldwide citation)

A method of manufacture of a Super Steep Retrograde Well Field Effect Transistor device starts with an SOI layer formed on a substrate, e.g. a buried oxide layer. Thin the SOI layer to form an ultra-thin SOI layer. Form an isolation trench separating the SOI layer into N and P ground plane regions. ...

Fariborz Assaderaghi, Tze Chiang Chen, K Paul Muller, Edward Joseph Nowak, Devendra Kumar Sadana, Ghavam G Shahidi: Double SOI device with recess etch and epitaxy. International Business Machines Corporation, H Daniel Schnurmann, Scully Scott Murphy & Presser, August 13, 2002: US06432754 (103 worldwide citation)

The present invention provides various methods for forming a ground-plane SOI device which comprises at least a field effect transistor formed on a top Si-containing surface of a silicon-on-insulator (SOI) wafer; and an oxide region present beneath the field effect transistor, located in an area bet ...

Byoung H Lee, Effendi Leobandung, Ghavam G Shahidi: Integration of dual workfunction metal gate CMOS devices. International Business Machines Corporation, Joseph P Abate, November 25, 2003: US06653698 (86 worldwide citation)

A dual work function CMOS metal gate device provides a composite metal gate electrode structure. The composite metal gate structure includes a bulk metal and a thin metal layer having an appropriate work function for the transistor type and desired threshold voltage, V

Fariborz Assaderaghi, Louis Lu Chen Hsu, Jack A Mandelman, Ghavam G Shahidi, Steven H Voldman: Silicon-on-insulator body-coupled gated diode for electrostatic discharge (ESD) and analog applications. International Business Machines Corporation, Joseph P Abate, Schmeiser Olsen & Watts, September 22, 1998: US05811857 (72 worldwide citation)

A body-coupled gated diode for silicon-on-insulator (SOI) technology is disclosed. The body-coupled gated diode is formed from an SOI field-effect transistor (FET). The body, gate and drain of the SOI FET are tied together, forming the first terminal of the diode. The source of the SOI FET forms the ...

Bahman Hekmatshoartabari, Tak H Ning, Ghavam G Shahidi, Davood Shahrjerdi: Active matrix using hybrid integrated circuit and bipolar transistor. International Business Machines Corporation, Tutunjian & Bitetto P C, Louis Percello, December 9, 2014: US08906755 (49 worldwide citation)

A hybrid integrated circuit device includes a semiconductor-on-insulator substrate having a base substrate, a semiconductor layer and a dielectric layer disposed therebetween, the base substrate being reduced in thickness. First devices are formed in the semiconductor layer, the first devices being ...

Stephen W Bedell, Kangguo Cheng, Bruce B Doris, Ali Khakifirooz, Devendra K Sadana, Ghavam G Shahidi: Strained CMOS device, circuit and method of fabrication. International Business Machines Corporation, Tutunjian & Bitetto P C, Louis J Percello Esq, May 1, 2012: US08169025 (36 worldwide citation)

A semiconductor device and fabrication method include a strained semiconductor layer having a strain in one axis. A long fin and a short fin are formed in the semiconductor layer such that the long fin has a strained length along the one axis. An n-type transistor is formed on the long fin, and a p- ...

Ghavam G Shahidi, Denny D Tang, Yuan Taur: SOI lateral bipolar transistor with edge-strapped base contact and method of fabricating same. International Business Machines, Scully Scott Murphy & Presser, March 29, 1994: US05298786 (27 worldwide citation)

A silicon-on-insulator lateral bipolar transistor having an edge-strapped base contact is disclosed. A thin layer of oxide is deposited on a silicon-on-insulator structure and a layer of polysilicon is deposited on the thin oxide layer that is patterned and etched to form an extrinsic base region of ...