1
Martin Vorbach, Frank May, Dirk Reichardt, Frank Lier, Gerd Ehlers, Armin Nückel, Volker Baumgarte, Prashant Rao, Jens Oertel: Logic cell array and bus system. Pact XPP Technologies, Kenyon & Kenyon, September 29, 2009: US07595659 (46 worldwide citation)

A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separa ...


2
Martin Vorbach, Volker Baumgarte, Gerd Ehlers, Frank May, Armin Nückel: Pipeline configuration unit protocols and communication. PACT XPP Technologies, Kenyon & Kenyon, February 21, 2006: US07003660 (22 worldwide citation)

An example method of controlling a data processing system having a cellular structure. The method includes transmitting a first configuration word to a first processing unit in the cellular structure. The method also includes processing data with the first processing unit in accordance with the firs ...


3
Martin Vorbach, Frank May, Dirk Reichardt, Frank Lier, Gerd Ehlers, Armin Nückel, Volker Baumgarte, Prashant Rao, Jens Oertel: Logical cell array and bus system. PACT XPP TECHNOLOGIES, Edward P Heller III, June 2, 2015: US09047440 (5 worldwide citation)

A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separa ...


4
Martin Vorbach, Volker Baumgarte, Gerd Ehlers, Frank May, Armin Nückel: Pipeline configuration protocol and configuration unit communication. Kenyon & Kenyon, October 30, 2012: US08301872 (4 worldwide citation)

An example method of controlling a data processing system having a cellular structure. The method includes transmitting a first configuration word to a first processing unit in the cellular structure. The method also includes processing data with the first processing unit in accordance with the firs ...


5
Martin Vorbach, Frank May, Dirk Reichardt, Frank Lier, Gerd Ehlers, Armin Nückel, Volker Baumgarte, Prashant Rao, Jens Oertel: Logic cell array and bus system. Bechen PLLC, June 25, 2013: US08471593 (2 worldwide citation)

A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separa ...


6
Martin Vorbach, Frank May, Dirk Reichardt, Frank Lier, Gerd Ehlers, Armin Nückel, Volker Baumgarte, Prashant Rao, Jens Oertel: Logic cell array and bus system. Kenyon & Kenyon, November 15, 2011: US08058899 (1 worldwide citation)

A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separa ...


7
Martin Vorbach, Volker Baumgarte, Gerd Ehlers, Frank May, Armin Nückel: Pipeline configuration protocol and configuration unit communication. Bechen PLLC, June 18, 2013: US08468329

In a method of synchronizing data processing of processor arrangement, responsive to reaching, during execution of a program, a barrier included in a program sequence, the processor arrangement halts the program execution until it is determined that all instructions preceding the barrier in the prog ...


8
Martin Vorbach, Volker Baumgarte, Gerd Ehlers: Bus systems and reconfiguration methods. Kenyon & Kenyon, February 28, 2012: US08127061

A processor chip includes data processing elements that each has dedicated to it a respective switch for dynamically establishing an interconnection between the data processing elements conditional upon verification of a validity of the interconnection, which verification is automatically performed ...


9
Martin Vorbach, Frank May, Dirk Reichardt, Frank Lier, Gerd Ehlers, Armin Nückel, Volker Baumgarte, Prashant Rao, Jens Oertel: Data processor chip with flexible bus system. PACT XPP TECHNOLOGIES, Edward P Heller III, February 9, 2016: US09256575

A data processor chip having a two-dimensional array of arithmetic logic units and memory where the arithmetic logic units are in communication with memory units in one dimension and with other arithmetic units in a second.


10
Martin Vorbach, Frank May, Dirk Reichardt, Frank Lier, Gerd Ehlers, Armin Nückel, Volker Baumgarte, Prashant Rao, Jens Oertel: Array processor having a segmented bus system. PACT XPP TECHNOLOGIES, Edward P Heller III, April 18, 2017: US09626325

An array processor on integrated circuit chip. The array processor has a plurality of memories and a segmented bus system, wherein each segment is selectively connectable to other segments and wherein each segment has a plurality of selectable data paths. A segment is connected to each array process ...