1
William R Wheeler, George M Uhler: Pipeline bubble compression in a computer system. Digital Equipment Corporation, Arnold White & Durkee, May 28, 1991: US05019967 (41 worldwide citation)

Bubble compression in a pipelined central processing unit (CPU) of a computer system is provided. A bubble represents a stage in the pipeline that cannot perform any useful work due to the lack of data from an earlier pipeline stage. When a particular pipeline stage has stalled, the CPU instructions ...


2
Douglas E Sanders, George M Uhler, John F Brown III: Pipelined digital CPU with deadlock resolution. Digital Equipment Corporation, Arnold White & Durkee, April 9, 1991: US05006980 (32 worldwide citation)

A pipelined CPU employs separate microinstruction pipelines for the execution unit and memory management unit. Deadlocks can occur in a pipelined CPU when there is data dependency in two consecutive instructions. The later instruction may stall the pipeline if operands fetched by an earlier instruct ...


3
William J Grundmann, George M Uhler, Richard E Calcagni: Digital processor with bit mask for counting registers for fast register saves. Digital Equipment Corporation, Arnold White & Durkee, June 14, 1994: US05321823 (31 worldwide citation)

A high-performance, pipelined CPU in which an improved method is used for saving registers in memory upon the occurrence of a procedure CALL or RETURN. The registers which need to be saved are defined by a bit-mask, and the number of bits is counted by a hardwired circuit, in each machine cycle, pro ...


4
Richard T Witek, George M Uhler: Load/store with write-intent for write-back caches. Digital Equipment Corporation, Kenyon & Kenyon, August 27, 1991: US05043886 (30 worldwide citation)

A method for reading data blocks from main memory by central processing units in a multiprocessor system containing write-back caches. Load or gather instructions contain a write-intent flag. The status of the write-intent flag is determined. It is also determined whether a data block requested in t ...


5
William J Grundmann, William C Madden, George M Uhler: Microinstruction addressing in high-speed CPU. Digital Equipment Corporation, Arnold White & Durkee, June 11, 1991: US05023828 (26 worldwide citation)

A memory stack used for storing microinstruction addresses in a pipelined CPU is constructed as a last-in, first-out memory using a stack pointer which applies a read control to one location of the stack and applies a write control to the next higher location. An unconditional read and write is done ...


6
Robert Dickson, W Hugh Durdan, George M Uhler: Method and apparatus for optimizing inter-processor instruction transfers. Digital Equipment Corporation, Arnold White & Durkee, January 30, 1990: US04897779 (13 worldwide citation)

A protocol for transferring instructions between asynchronous processors in a computer system is provided. Each instruction transfer requires the transfer of an opcode and a variable number of operands. The transfer is accomplished via a bus which interconnects the processors. The opcode and operand ...


7
George M Uhler, John F Brown III: Operand specifier processing by grouping similar specifier types together and providing a general routine for each. Digital Equipment Corporation, Arthur W Fisher, Denis G Maloney, Joanne N Pappas, March 19, 1996: US05500947 (11 worldwide citation)

A method of specifying the operands for a microcoded CPU employs a combination of a set of microinstruction routines for generic operand modes, along with hardware primitives for selecting various specific types of operand treatment. Decoding of a machine-level instruction produces an entry point fo ...


8
George M Uhler, George G Mills: Dynamic microbranching with programmable hold on condition, to programmable dynamic microbranching delay minimization. Digital Equipment Corporation, Mark J Casey, Denis G Maloney, Arthur W Fisher, December 31, 1996: US05590293 (6 worldwide citation)

A pipelined, microcoded CPU employs conditional branching in microcode execution Data path conditions produced by one microinstruction are used in the selection of a following microinstruction. In high-performance systems, multiple cycle microbranch latency requires that the generation of microbranc ...