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Steve S Chen, Frederick J Simmons, George A Spix, Jimmie R Wilson, Edward C Miller, Roger E Eckert, Douglas R Beard: Cluster architecture for a highly parallel scalar/vector multiprocessor system. Supercomputer Systems Partnership, Patterson & Keough, March 23, 1993: US05197130 (224 worldwide citation)

A cluster architecture for a highly parallel multiprocessor computer processing system is comprised of one or more clusters of tightly-coupled, high-speed processors capable of both vector and scalar parallel processing that can symmetrically access shared resources associated with the cluster, as w ...


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Gregory G Gaetner, George A Spix, Diane M Wengelski, Keith J Thompson: System having integrated dispatcher for self scheduling processors to execute multiple types of processes. Cray Research, Schwegman Lundberg & Woessner, September 19, 1995: US05452452 (107 worldwide citation)

Method for enabling each of several processors in a multi-processing operating system to schedule processes it will execute without a supervisory scheduler. The processes are executed on the basis of priorities assigned to the processes. More than one processor can schedule processes simultaneously ...


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Douglas R Beard, Andrew E Phelps, Michael A Woodmansee, Richard G Blewett, Jeffrey A Lohman, Alexander A Silbey, George A Spix, Frederick J Simmons, Don A Van Dyke: Scalar/vector processor. Cray Research, Schwegman Lundberg & Woessner, July 4, 1995: US05430884 (95 worldwide citation)

The present invention is an improved high performance scalar/vector processor. In the preferred embodiment, the scalar/vector processor is used in a multiprocessor system. The scalar/vector processor is comprised of a scalar processor for operating on scalar and logical instructions, including a plu ...


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Steve S Chen, Douglas R Beard, George A Spix, Edward C Priest, John M Wastlick, James M VanDyke: Method and apparatus for a unified parallel processing architecture. Cray Research, Schwegman Lundberg & Woessner, June 27, 1995: US05428803 (70 worldwide citation)

A unified parallel processing architecture connects together an extendible number of clusters of multiple numbers of processors to create a high performance parallel processing computer system. Multiple processors are grouped together into four or more physically separable clusters, each cluster hav ...


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Robert E Strout II, George A Spix, Jon A Masamitsu, David M Cox, Gregory G Gaertner, Diane M Wengelski, Keith J Thompson: Dual level scheduling of processes to multiple parallel regions of a multi-threaded program on a tightly coupled multiprocessor computer system. Cray Research, Daniel J Kluth, August 16, 1994: US05339415 (54 worldwide citation)

On a tightly coupled multiprocessor computer system, the multiple parallel regions of a multithreaded applications program can execute simultaneously as multiple threads on a plurality of processors. Furthermore, a plurality of multithreaded programs may run simultaneously. The current invention use ...


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Steve S Chen, Frederick J Simmons, George A Spix, Jimmie R Wilson, Edward C Miller, Roger E Eckert, Douglas R Beard: Interleaved memory access system having variable-sized segments logical address spaces and means for dividing/mapping physical address into higher and lower order addresses. Cray Research, Schwegman Lundberg Woessner & Kluth P A, October 1, 1996: US05561784 (52 worldwide citation)

A method of accessing common memory in a cluster architecture for a highly parallel multiprocessor scaler/factor computer system using a plurality of segment registers in which is first determined whether a logical address is within a start and end range as defined by the segment registers and then ...


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George A Spix, Glen L Collier, G Joseph Throop, David L Clounch, Cris J Rhea, Douglas R Beard: Control and maintenance subsystem network for use with a multiprocessor computer system. Supercomputer Systems Partnership, Patterson & Keough, October 12, 1993: US05253359 (52 worldwide citation)

Methods and apparatus for a maintenance and control system for sensing and controlling the numerous sections of a highly parallel multiprocessor system. The control and maintenance system communicates with all processors, all peripheral systems, all user interfaces to the multiprocessor system, a sy ...


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Edward C Miller, George A Spix, Anthony R Schooler, Douglas R Beard, Alexander A Silbey, Andrew E Phelps: Dedicated centralized signaling mechanism for selectively signaling devices in a multiprocessor system. Supercomputer Systems Partnership, Patterson & Keough, August 24, 1993: US05239629 (41 worldwide citation)

A signaling mechanism for sending and receiving signals to and from any one of all of a plurality of devices, including peripheral controllers and processors, in a multiprocessor system. The signaling mechanism includes two switches, a first switch routing a signal command generated by the device to ...



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