1
Mark Justin Moore, Gavin J Stark: Method and apparatus for source rate pacing in an ATM network. Virata, Pennie & Edmonds, September 14, 1999: US05953336 (80 worldwide citation)

A method and apparatus for scheduling the transmission of cells onto an network, or other packet switching network, is disclosed. The central feature of the scheduling mechanism is a multi-functional timing ring which accommodates both preallocated static scheduling for use with CBR and real-time VB ...


2
Gavin J Stark: Picoengine instruction that controls an intelligent packet data register file prefetch function. Netronome Systems, Imperium Patent Works, T Lester Wallace, Mark D Marrello, December 13, 2016: US09519484 (12 worldwide citation)

A multi-processor includes a pool of processors and a common packet buffer memory. Bytes of packet data of a packet are stored in the packet buffer memory. Each processor has an intelligent packet data register file. One processor is tasked with processing the packet, and its packet data register fi ...


3
Gavin J Stark: Transactional memory that supports a put with low priority ring command. Netronome Systems Incorporated, Imperium Patent Works, T Lester Wallace, Mark D Marrello, March 3, 2015: US08972630 (7 worldwide citation)

A transactional memory (TM) includes a control circuit pipeline and an associated memory unit. The memory unit stores a plurality of rings. The pipeline maintains, for each ring, a head pointer and a tail pointer. A ring operation stage of the pipeline maintains the pointers as values are put onto a ...


4
Gavin J Stark, Stuart C Wray: Method of generating subflow entries in an SDN switch. Netronome Systems, Imperium Patent Works, T Lester Wallace, Mark D Marrello, October 11, 2016: US09467378 (4 worldwide citation)

A method involving a Software-Defined Networking (SDN) switch. A packet is received onto a SDN switch via a NFX circuit. The NFX circuit determines that the packet matches no flow entry stored in any flow table in the NFX circuit and forwards the packet to a NFP circuit. The NFP circuit determines t ...


5
Gavin J Stark, John Wishneusky: Multiple coprocessor architecture to process a plurality of subtasks in parallel. Intel Corporation, Blakley Sokoloff Taylor & Zafman, February 28, 2006: US07007156 (2 worldwide citation)

A programmed state processing machine architecture and method that provides improved efficiency for processing data manipulation tasks. In one embodiment, the processing machine comprises a control engine and a plurality coprocessors, a data memory, and an instruction memory. A sequence of instructi ...


6
Gavin J Stark, Stuart C Wray: SDN protocol message handling within a modular and partitioned SDN switch. Netronome Systems, Imperium Patent Works, T Lester Wallace, Mark D Marrello, November 22, 2016: US09503372 (2 worldwide citation)

An integrated circuit includes ingress ethernet ports and egress ethernet ports. A second ingress ethernet port is configurable to operate in a selected one of a command mode and a data mode. The ingress ethernet port does not power up in the command mode and can only be put into the command mode as ...


7
Gavin J Stark, John Wishneusky: MAC bus interface. Intel Corporation, Blakely Sokoloff Taylor & Zafman, November 8, 2005: US06963535 (2 worldwide citation)

A Media Access Control (MAC) Bus interface definition and multiplexor scheme that may be implemented to provide chip layout-insensitive connections between a number of communication physical layer port entities and a single buffer manager or communications controller entity, utilizing a set of indep ...


8
Gavin J Stark, Steven W Zagorianakos, Ron L Swartzentruber, Richard P Bouley: Flow control using a local event ring in an island-based network flow processor. Netronome Systems Incorporated, Imperium Patent Works, T Lester Wallace, Mark D Marrello, January 6, 2015: US08929376 (2 worldwide citation)

An island-based network flow processor (IB-NFP) integrated circuit includes islands organized in rows. A configurable mesh event bus extends through the islands and is configured to form a local event ring. The configurable mesh event bus is configured with configuration information received via a c ...


9
Gavin J Stark: Transactional memory that performs an atomic metering command. NETRONOME SYSTEMS INCORPORATED, Imperium Patent Works, T Lester Wallace, Mark D Marrello, June 30, 2015: US09069603 (1 worldwide citation)

A transactional memory (TM) receives an Atomic Metering Command (AMC) across a bus from a processor. The command includes a memory address and a meter pair indicator value. In response to the AMC, the TM pulls an input value (IV). The TM uses the memory address to read a word including multiple cred ...


10
Gavin J Stark: Intelligent packet data register file that prefetches data for future instruction execution. Netronome Systems, Imperium Patent Works, T Lester Wallace, Mark D Marrello, August 16, 2016: US09417916 (1 worldwide citation)

A multi-processor includes a pool of processors and a common packet buffer memory. Bytes of packet data of a packet are stored in the packet buffer memory. Each processor has an intelligent packet data register file. One processor is tasked with processing the packet, and its packet data register fi ...