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Hamza Yilmaz, Daniel Calafut, Christopher Boguslaw Kocon, Steven P Sapp, Dean E Probst, Nathan L Kraft, Thomas E Grebs, Rodney S Ridley, Gary M Dolny, Bruce D Marchant, Joseph A Yedinak: Trench-gate field effect transistors and methods of forming the same. Fairchild Semiconductor Corporation, Townsend and Townsend and Crew, March 17, 2009: US07504303 (52 worldwide citation)

A method for forming a shielded gate field effect transistor includes the following steps. Trenches extending into a silicon region are formed using a mask that includes a protective layer. A shield dielectric layer lining sidewalls and bottom of each trench is formed. A shield electrode is formed i ...


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Fu Lung Hseuh, Alfred C Ipri, Gary M Dolny, Roger G Stewart: Method for fabricating a switching transistor having a capacitive network proximate a drift region. David Sarnoff Research Center, William J Burke, December 24, 1996: US05587329 (34 worldwide citation)

In an active matrix electroluminescent display, a pixel containing a grounded conductive electric field shield between an EL cell and the switching electronics for the EL cell. In a method of fabricating the pixel, first, an EL cell switching circuit is formed, then an insulating layer is formed ove ...


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Thomas E Grebs, Gary M Dolny: Semiconductor power device having a top-side drain using a sinker trench. Fairchild Semiconductor Corporation, Townsend and Townsend and Crew, April 1, 2008: US07352036 (31 worldwide citation)

A semiconductor power device includes a substrate of a first conductivity type and an epitaxial layer of the first conductivity type over and in contact with the substrate. A first trench extends into and terminates within the epitaxial layer. A sinker trench extends from the top surface of the epit ...


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Jun Zeng, Gary M Dolny, Christopher B Kocon, Linda S Brush: Power MOS device with buried gate. Fairchild Semiconductor Corporation, Thomas R FitzGerald Esq, October 28, 2003: US06638826 (27 worldwide citation)

An MOS power device a substrate comprises an upper layer having an upper surface and an underlying drain region, a well region of a first conductance type disposed in the upper layer over the drain region, and a plurality of spaced apart buried gates, each of which comprises a trench that extends fr ...


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Nathan L Kraft, Ashok Challa, Steven P Sapp, Hamza Yilmaz, Daniel Calafut, Dean E Probst, Rodney S Ridley, Thomas E Grebs, Christopher B Kocon, Joseph A Yedinak, Gary M Dolny: Trench FET with improved body to gate alignment. Fairchild Semiconductor Corporation, Townsend and Townsend and Crew, August 26, 2008: US07416948 (21 worldwide citation)

A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. Each trench is partially filled with one or more materials. A dual-pass angled implant is carried out to implant dopants of a second conductivity type into the semiconductor re ...


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Jun Zeng, Gary M Dolny, Christopher B Kocon, Linda S Brush: Power MOS device with buried gate and groove. Fairchild Semiconductor Corporation, Thomas R Fitzgerald, September 3, 2002: US06445035 (21 worldwide citation)

An MOS power device a substrate comprises an upper layer having an upper surface and an underlying drain region, a well region of a first conductance type disposed in the upper layer over the drain region, and a plurality of spaced apart buried gates, each of which comprises a trench that extends fr ...


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Joseph A Yedinak, Jon Gladish, Sampat Shekhawat, Gary M Dolny, Praveen Muraleedharan Shenoy, Douglas Joseph Lange, Mark L Rinehimer: Quick punch through IGBT having gate-controllable DI/DT and reduced EMI during inductive turn off. Fairchild Semiconductor Corporation, Thomas R FitzGerald Esq, Laurence S Roach Esq, December 14, 2004: US06831329 (16 worldwide citation)

A quick punch-through integrated gate bipolar transistor (IGBT) includes a drift region and a gate. The drift region has a drift region dopant concentration and a drift region thickness. The gate has a gate capacitance. The drift region dopant concentration, drift region thickness and gate capacitan ...


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Jifa Hao, Rodney S Ridley, Gary M Dolny: Dense trench MOSFET with decreased etch sensitivity to deposition and etch processing. Fairchild Semiconductor Corporation, Robert D Lott Esq, Hiscock & Barclay, October 14, 2008: US07436021 (15 worldwide citation)

A power MOSFET 100 has a source metal 112 that contacts silicided source regions 114 through vias 160 etched in an insulating layer 200. The silicide layer 225 provides for a relatively small but highly conductive contact and thus reduces RDSON. The insulating material may be any suitable material i ...