1
John Xidos, Ross MacDougall, David Carrigan, Gary Hammond, Pamela Little, Bruce Reid: Distributed gaming system. Tech Link International Entertainment, Roylance Abrams Berdo & Goodman, December 22, 1998: US05851149 (762 worldwide citation)

The Distributed Gaming System provides a user with remote location gaming, for example from within a hotel room. Using the room's television and a remote control, the user, such as a hotel guest, is able to play games similar to those available on a Video Lottery Terminal. The games are displayed on ...


2
Donald Alpert, Gary Hammond: Method and apparatus for providing efficient software debugging. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 15, 1997: US05621886 (56 worldwide citation)

A method and apparatus for the separate enablement of debug events during the execution of operating system routines and non-operating system routines. According to one aspect of the invention, a processor is described which may operate in a first mode and a second mode. While operating in the first ...


3
Donald Alpert, Gary Hammond: Method and apparatus for providing address breakpoints, branch breakpoints, and single stepping. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 14, 1998: US05740413 (52 worldwide citation)

A method and apparatus for providing address breakpoints, branch breakpoints, and single stepping is described. According to one aspect of the invention, a processor is provided which generally includes an execution unit, a first storage area, and an address breakpoint unit. The execution unit recog ...


4
Gary Hammond, Donald Alpert, Kevin Kahn, Harsh Sharangpani: Method and apparatus for providing two system architectures in a processor. Intel Corporation, Blakely Sokoloff Taylor & Zafman, June 30, 1998: US05774686 (46 worldwide citation)

A processor having two system configurations is provided. The apparatus generally includes an instruction set unit, a system unit, an internal bus, and a bus unit. The instruction set unit, the system unit, and the bus unit are coupled together by the internal bus. The system unit is capable of sele ...


5
Gary Hammond, Donald Alpert, Kevin Kahn, Harsh Sharangpani: Method and apparatus for providing event handling functionality in a computer system. Intel Corporation, Blakely Sokoloff Taylor & Zafman, June 18, 2002: US06408386 (37 worldwide citation)

Method And Apparatus for Providing Event Handling Functionality in a Computer System. According to one embodiment of the invention, a computer system includes an instruction set unit and an event handling unit in a processor, as well as a first plurality of event handlers that includes a first event ...


6
Nazar Zaidi, Gary Hammond, Ken Shoemaker: Method and apparatus for scheduling instructions in waves. Intel Corporation, Blakely Sokoloff Taylor & Zafman, January 18, 2000: US06016540 (28 worldwide citation)

In a microprocessor, an Instruction scheduler 30 includes a dependency matrix 36 and a waiting buffer 34. A dependency determination unit 32 receives instructions to be executed, forwards the instructions to the waiting buffer 34, determines if any dependency exists between the instructions, and for ...


7
Gary Hammond, Donald Alpert, Kevin Kahn, Harsh Sharangpani: Address translation with/bypassing intermediate segmentation translation to accommodate two different instruction set architecture. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 17, 2001: US06219774 (27 worldwide citation)

A Method and Apparatus for Providing Memory Management and Event Handling Functionality in a Computer System. According to one embodiment of the invention, a processor comprises an instruction set unit, a segmentation unit, and a paging unit. The instruction set unit is to support a first and second ...


8
Nazar Zaidi, Gary Hammond, Ken Shoemaker, Jeff Baxter: Dependency matrix. Intel Corporation, Charles A Mirho, May 16, 2000: US06065105 (25 worldwide citation)

In a microprocessor, an instruction scheduler 30 includes a dependency matrix 36 and a waiting buffer 34. A dependency determination unit 32 receives instructions to be executed, forwards the instructions to the waiting buffer 34, determines if any dependency exists between the instructions, and for ...


9
Nazar Abbas Zaidi, Gary Hammond, Kin Yip Liu, Tse Yu Yeh: Microcode upgrade and special function support by executing RISC instruction to invoke resident microcode. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 1, 2003: US06542981 (25 worldwide citation)

A method and apparatus for invoking microcode instructions resident on a processor by executing a special RISC instruction on the processor such that special functions are provided. In one embodiment, the special function invoked may be a feature of the processor not included in the processor's ...


10
Nhon T Quach, Gary Hammond, Kin Yip Liu: Preventing access to secure area of a cache. Intel Corporation, Kenyon & Kenyon, May 28, 2002: US06397301 (22 worldwide citation)

Information in a cache that is coupled to a processor is secured by recording the location in the cache of information that is being secured, and performing a cache avoidance procedure instead of allowing the instruction to access the area of the cache containing the information being secured.



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