1
Valeri Popescu, Merle A Schultz, Gary A Gibson, John E Spracklen, Bruce D Lightner: Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched. Townsend and Townsend and Crew, January 23, 1996: US05487156 (177 worldwide citation)

A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if ...


2
Valeri Popescu, Merle A Schultz, Gary A Gibson, John E Spracklen, Bruce D Lightner: Processor architecture having out-of-order execution, speculative branching, and giving priority to instructions which affect a condition code. Hyundai Electronics America, Townsend and Townsend and Crew, April 29, 1997: US05625837 (120 worldwide citation)

A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if ...


3
Valeri Popescu, Merle A Schultz, Gary A Gibson, John E Spracklen, Bruce D Lightner: Processor architecture supporting multiple speculative branching. Hyundai Electronics America, Townsend and Townsend and Crew, October 1, 1996: US05561776 (115 worldwide citation)

A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if ...


4
Valeri Popescu, Merle A Schultz, Gary A Gibson, John E Spracklen, Bruce D Lightner: Processor architecture supporting multiple speculative branches and trap handling. Hyundai Electronics America, Townsend and Townsend and Crew, January 7, 1997: US05592636 (75 worldwide citation)

A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if ...


5
Valeri Popescu, Merle A Schultz, Gary A Gibson, John E Spracklen, Bruce D Lightner: Processor architecture providing out-of-order execution. Hyundai Electronics America, Townsend and Townsend and Crew, May 6, 1997: US05627983 (74 worldwide citation)

A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if ...


6
Valeri Popescu, Merle A Schultz, Gary A Gibson, John E Spracklen, Bruce D Lightner: Processor architecture providing speculative, out of order execution of instructions. Hyundai Electronics America, Pennie & Edmonds, January 13, 1998: US05708841 (70 worldwide citation)

A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if ...


7
Valeri Popescu, Merle A Schultz, Gary A Gibson, John E Spracklen, Bruce D Lightner: Processor architecture providing speculative, out of order execution of instructions and trap handling. Hyundai Electronics America, Pennie & Edmonds, November 3, 1998: US05832293 (69 worldwide citation)

A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if ...


8
Valeri Popescu, Merle A Schultz, Gary A Gibson, John E Spracklen, Bruce D Lightner: Processor architecture supporting speculative, out of order execution of instructions including multiple speculative branching. Hyundai Electronics America, Pennie & Edmonds, August 18, 1998: US05797025 (63 worldwide citation)

A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if ...


9
Gary A Gibson: AFM version of diode-and cathodoconductivity-and cathodoluminescence-based data storage media. Hewlett Packard Company, January 14, 2003: US06507552 (23 worldwide citation)

An ultra-high-density data storage device including at least one energy-channeling component and a storage medium that usually includes at least one rectifying junction region. The energy-channeling component is generally capable of emitting such energies as, but not limited to, thermal, optical and ...


10
Andrew S Podgorski, Gary A Gibson: Broadband antennas and electromagnetic field simulators. Andrew Podgorski, Jones Tullar & Cooper, August 8, 1995: US05440316 (19 worldwide citation)

A structure for use in an antenna or as a broadband electromagnetic field simulator, having an open horn TEM waveguide coupled to launch energy in a strip line formed between a forwardly extending plate section and a ground plane. When used as a simulator the test volume is located outside the horn ...