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Barry R Borgerson, Garold S Tjaden, Merlin L Hanson: Microprogrammable computer utilizing concurrently operating processors. Sperry Corporation, Howard P Terry, Albert B Cooper, April 22, 1980: US04199811 (45 worldwide citation)

A microprogrammable CPU for a computer utilizes an architecture wherein macro instructions of the computer repertoire are executed by micro instruction routines stored in a control store memory. The micro instruction routines are comprised of micro instruction words for controlling the micro operati ...


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Barry R Borgerson, Garold S Tjaden, Merlin L Hanson: Digital computer with overlapped operation utilizing conditional control to minimize time losses. Sperry Corporation, Howard P Terry, Albert B Cooper, July 1, 1980: US04210960 (37 worldwide citation)

A computer which is configured to perform its operations in overlapped fashion. During each computer cycle the next instruction is fetched, the function designated by the previous instruction is executed, and values are stored that were computed with respect to the instruction previous to the one be ...


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Barry R Borgerson, Garold S Tjaden, Merlin L Hanson: Table driven decision and control logic for digital computers. Sperry Corporation, Howard P Terry, Albert B Cooper, December 2, 1980: US04237532 (10 worldwide citation)

Decision and control logic for use in digital computers that operate in cycles provides binary valued decision signals for effecting decisional control within the computer such as that utilized in conditional branching. The decision signals are provided in accordance with binary valued control funct ...


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Barry R Borgerson, Garold S Tjaden: Ones complement subtractive arithmetic unit utilizing twos complement arithmetic circuits. Sperry Rand Corporation, Howard P Terry, Albert B Cooper, July 4, 1978: US04099248 (9 worldwide citation)

The one's complement subtractive arithmetic unit comprises a parallel adder with a connection for providing an end-around carry, from the carry output of the most significant stage to the carry input of the least significant stage. The parallel adder is implemented utilizing multiple bit LSI ALU chi ...


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