1
Daniel M McCarthy, Joseph C Circello, Gabriel R Munguia, Nicholas J Richardson: Coherent cache structures and methods. Edgcore Technology, Cahill Sutton & Thomas, May 22, 1990: US04928225 (63 worldwide citation)

A multiprocessing system includes a cache coherency technique that ensures that every access to a line of data is the most up-to-date copy of that line without storing cache coherency status bits in a global memory and any reference thereto. An operand cache includes a first directory which directly ...


2
Daniel M McCarthy, Joseph C Circello, Gabriel R Munguia, Nicholas J Richardson: Coherent cache structures and methods. Edge Computer Corporation, Cahill Sutton & Thomas, July 2, 1991: US05029070 (60 worldwide citation)

A multiprocessing system includes a cache coherency technique that ensures that every access to a line of data is the most up-to-date copy of that line without storing cache coherency status bits in a global memory and any reference thereto. An operand cache includes a first directory which directly ...


3
Gabriel R Munguia, Ned D Garinger, Nicholas J Richardson: Combined consective byte update buffer. VLSI Technology, Wagner Murabito & Hao, April 6, 1999: US05892978 (13 worldwide citation)

An apparatus and method for minimizing bus traffic by combining write operations is disclosed. The present invention detects the occurrence of consecutive byte updates to a common 32-bit block. This is accomplished by using comparators to examine the addresses of consecutive write operations. If it ...


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Lonnie Goff, Gabriel R Munguia, Brian Logsdon: Hardware register access via task tag ID. NXP, December 1, 2009: US07627869 (1 worldwide citation)

A computer-based software task management system includes an index register configured to store a data register pointer for pointing to a data register. A Task ID register is coupled to the index register and configured to store a Task ID keyed to the index register. A Task ID memory is coupled to t ...


6
Peter R Munguia, Gabriel R Munguia: Error rate based power management of a high-speed serial link. Intel Corporation, Intel Corporation, c o INTELLEVATE, February 28, 2008: US20080049716-A1

A method, circuit, and system are disclosed. In one embodiment, the method comprises dynamically adjusting the output voltage of the output drivers of one side of a bi-directional serial link down to the lowest voltage level that is able to maintain compliance with the error rate allowance threshold ...


7
Peter R Munguia, Gabriel R Munguia: Flow control credit synchronization. Intel Corporation, June 23, 2005: US20050137966-A1

Machine-readable media, methods, and apparatus are described to maintain synchronization of redundant devices. In one embodiment, a transmitter sends data packets to a receiver via a primary channel. Further, the transmitter may throttle data packet transfers on the primary channel based upon credit ...


8
Lonnie Goff, Gabriel R Munguia, Brian Logsdon: Hardware Register Access Via Task Tag Id. Nxp, Nxp Intellectual Property Department, August 28, 2008: US20080209427-A1

A computer-based software task management system (100) includes an index register (130) configured to store a data register pointer for pointing to a data register (150). A Task ID register (110) is coupled to the index register and configured to store a Task ID keyed to the index register. A Task I ...


9
Lonnie C Goff, Gabriel R Munguia: Selective access to multiple registers having a common name. Woodard Emhardt Naughton Moriarty and McNett, Bank One Center Tower, December 5, 2002: US20020179719-A1

Among the embodiments of the present invention is a processor (22) having a number of registers in a register bank (50). The registers include a general purpose register (52a) and a stack pointer register (52b) having a common register name. Processor (22) includes logic responsive to programming to ...