1
Gabriel Calvin T, Lyons Christopher F, Plat Marina V, Subramanian Ramkumar: Contact etch resistant spacers. Advanced Micro Devcies, Gabriel Calvin T, Lyons Christopher F, Plat Marina V, Subramanian Ramkumar, sDRAKE Paul S, July 7, 2005: WO/2005/062372

An apparatus and a method of fabricating a semiconductor device (10) including the steps of forming a gate dielectric layer (20) on a semiconductor substrate (12); forming a gate electrode (18) over the gate dielectric layer (20) wherein the gate electrode (20) defines a channel (22) interposed betw ...


2
Gabriel Calvin T, Subhash Nariani R: Wafer level prediction of thin oxide reliability. Vlsi Technology, WILLIAMS Gary S, August 1, 1996: WO/1996/023319

An IC wafer includes at least one pair of antenna structures (C1L-C2L, C1S-C2S) that each include a first conductive plate (50L, 50S) formed over thick field oxide (40), coupled to a second conductive plate (30L, 30S), formed over thin oxide (20). The plates have different areas but the same antenna ...


3
Wang Fei, Okada Lynne A, Subramanian Ramkumar, Gabriel Calvin T: A slot via filled dual damascene structure without middle stop layer and method for making the same. Advanced Micro Devices, RODDY Richard J, August 15, 2002: WO/2002/063676

An interconnect structure and method of forming the same in which a diffusion barrier/etch stop layer (22) is deposited over a conductive layer (20). An organic low k dielectric material (24) is deposited over the diffusion barrier/etch stop layer (22) to form a first dielectric layer (24). The firs ...


4
Gabriel Calvin T: Imminent endpoint detection for plasma etch system. Vlsi Technology, HICKMAN Paul L, January 23, 1992: WO/1992/001308

A method for detecting imminent end-point when plasma etching a dielectric layer (44) of a substrate (42) by monitoring the D.C. bias voltage of the cathode during the etching process. The D.C. bias voltage gives an indirect reading of the impedance of the substrate which changes appreciably just pr ...


5
Boardman William J, Chan David P Kwan, Chang Kuang Yeh, Gabriel Calvin T, Jain Vivek, Nariani Subhash R: Anti-fuse structures and methods for making same. Vlsi Technology, HICKMAN Paul L, March 18, 1993: WO/1993/005514

A method for making an anti-fuse structure characterized by the steps of forming a conductive base layer (10); forming an anti-fuse layer (20) over the base layer; patterning the anti-fuse layer to form an anti-fuse island (24a, 24b); forming an insulating layer (26) over the anti-fuse island; formi ...


6
Dimitrelis Dimitrios, Gabriel Calvin T, Dunton Samuel V: System and method for plasma etching endpoint detection. Vlsi Technology, WILLIAMS Gary S, March 23, 1995: WO/1995/008186

A plasma etching endpoint detection system (134) monitors two optical wavelengths during etching of a non-opaque dielectric film. A controller (160) coupled to the optical monitoring equipment (162) generates an endpoint detection signal corresponding to a predefined mathematical combination of the ...


7
Boardman William J, Chan David P Kwan, Chang Kuang Yeh, Gabriel Calvin T, Jain Vivek, Nariani Subhash R: Anti-fuse structures and methods for making same. Vlsi Technology, HICKMAN Paul L, February 18, 1993: WO/1993/003499

An anti-fuse structure characterized by a substrate (18), an oxide layer (46) formed over the substrate having an opening (48) formed therein, an amorphous silicon material (52) disposed within the opening and contacting the substrate, a conductive protective material (59), such as titanium tungsten ...


8
Boardman William J, Chan David P Kwan, Chang Kuang Yeh, Gabriel Calvin T, Jain Vivek, Nariani Subhash R: Anti-fuse structures and methods for making same. Vlsi Technology, HICKMAN Paul L, December 10, 1992: WO/1992/022088

An anti-fuse structure characterized by a substrate, an oxide layer (46) formed over the substrate having an opening (48) formed therein, an amorphous silicon material (52) disposed within the opening and contacting the substrate, and oxide spacers (64) lining the walls of a recess formed within the ...


9
Gabriel Calvin T: Method for moisture sealing integrated circuits using silicon nitride spacer protection of oxide passivation edges. Vlsi Technology, HICKMAN Paul L, May 13, 1993: WO/1993/009566

For passivation of an integrated circuit device, a film of silicon dioxide (32) is deposited over the integrated circuit device. A film of silicon nitride (33) is deposited over the film of silicon dioxide. The film of silicon nitride and the film of silicon dioxide are etched using a single passiva ...


10
Annapragada Rao V, Gabriel Calvin T, Weling Milind G: Semiconductor fabrication method and system. Koninklijke Philips Electronics, Annapragada Rao V, Gabriel Calvin T, Weling Milind G, July 27, 2000: WO/2000/044035

A gas phase planarization process for semiconductor wafers. The present invention comprises a system and method of dry planarization for a semiconductor wafer. For instance, the present invention includes a system adapted to effectively remove all, or a portion of, a layer of dielectric material of ...



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