1
G Glenn Henry, Terry Parks: Static branch prediction mechanism for conditional branch instructions. IP First, Richard K Huffman, James W Huffman, May 27, 2003: US06571331 (84 worldwide citation)

An apparatus and method are provided for accurately predicting the outcome of branch instructions prior to their execution by a pipeline microprocessor. The apparatus has a static branch predictor, a mandatory signal, and a biased prediction correlator. The static branch predictor provides a predict ...


2
G Glenn Henry, Arturo Martin de Nicolas, Daniel G Miner: Fuse array control for smart function enable. Integrated Device Technology, James W Huffman, March 30, 1999: US05889679 (79 worldwide citation)

An apparatus and method for smart configuration of functional blocks within a semiconductor device is provided. A fuse array contains a plurality of fuses that are blown in manufacturing to enable/disable functional blocks on the semiconductor device. A control unit reads the state of the fuses, and ...


3
Gerard M Col, G Glenn Henry, Rodney E Hooker: Compare branch instruction pairing within a single integer pipeline. IP First, Richard K Huffman, James W Huffman, November 11, 2003: US06647489 (38 worldwide citation)

An apparatus and method are provided for executing a combined compare-and-branch operation in a single integer pipeline microprocessor. Typically, the compare-and-branch operation is specified by two macro instructions. The first macro instruction, a compare macro instruction, directs the microproce ...


4
Darius D Gaskins, G Glenn Henry, Rodney E Hooker: Translation lookaside buffer that caches memory type information. IP First, E Alan Davis, James W Huffman, January 20, 2004: US06681311 (35 worldwide citation)

A translation lookaside buffer (TLB) that caches memory types of memory address ranges. A data unit includes a TLB which, in addition to caching page table entries including translated page base addresses of virtual page numbers as in a conventional TLB, also caches memory address range memory types ...


5
Gerard M Col, G Glenn Henry: Apparatus and method for branch target address calculation during instruction decode. IP First, Richard K Huffman, James W Huffman, August 22, 2000: US06108773 (31 worldwide citation)

An apparatus and method for improving the execution of conditional branch instructions is provided. A translator detects a conditional branch instruction during decode of the instruction, and provides a displacement to a target address calculator. The target address calculator calculates a target ad ...


6
G Glenn Henry, Dinesh K Jain, Terry Parks: Microprocessor with program-accessible re-writable non-volatile state embodied in blowable fuses of the microprocessor. VIA Technologies, E Alan Davis, James W Huffman, February 16, 2010: US07663957 (29 worldwide citation)

A microprocessor includes re-writeable non-volatile state (RNS) addressable by an instruction executed by the microprocessor that instructs the microprocessor to write a new value to the RNS. A plurality of fuses are each readable to determine whether the fuse is blown or unblown, in response to the ...


7
G Glenn Henry, Terry Parks: Hybrid branch predictor with improved selector table update mechanism. IP First, E Alan Davis, James W Huffman, April 15, 2003: US06550004 (29 worldwide citation)

A branch predictor for improving branch prediction accuracy is provided. The branch predictor includes global and local Agree dynamic branch predictors, one of which is selected for correlation with a static branch prediction made based upon a test type of a conditional branch instruction specifying ...


8
G Glenn Henry, Thomas C McDonald: Speculative hybrid branch direction predictor. IP First, E Alan Davis, James W Huffman, April 26, 2005: US06886093 (27 worldwide citation)

An apparatus for speculatively predicting the direction of a branch instruction in a pipelined microprocessor in a hybrid fashion. A branch target address cache (BTAC) stores a direction prediction about executed branch instructions. The BTAC is indexed by an instruction cache fetch address. The BTA ...


9
G Glenn Henry, Dinesh K Jain: Apparatus and method for override access to a secured programmable fuse array. VIA Technologies, Richard K Huffman, James W Huffman, August 14, 2012: US08242800 (26 worldwide citation)

An apparatus in an integrated circuit for re-enabling the use of precluded extended JTAG operations. The apparatus includes a JTAG control chain, a feature fuse, a machine specific register, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations ...


10
Darius D Gaskins, G Glenn Henry, Rodney E Hooker: Method and apparatus for resolving additional load misses and page table walks under orthogonal stalls in a single pipeline processor. I P First, E Alan Davis, James W Huffman, April 15, 2003: US06549985 (26 worldwide citation)

A data cache in an in-order single-issue microprocessor that detects cache misses generated by instructions behind a stalled instruction in the microprocessor pipeline and issues memory requests on the processor bus for the missing data so as to overlap with resolution of the stalled instruction, wh ...