An apparatus and method are provided for accurately predicting the outcome of branch instructions prior to their execution by a pipeline microprocessor. The apparatus has a static branch predictor, a mandatory signal, and a biased prediction correlator. The static branch predictor provides a predict ...
An apparatus and method for smart configuration of functional blocks within a semiconductor device is provided. A fuse array contains a plurality of fuses that are blown in manufacturing to enable/disable functional blocks on the semiconductor device. A control unit reads the state of the fuses, and ...
An apparatus and method are provided for executing a combined compare-and-branch operation in a single integer pipeline microprocessor. Typically, the compare-and-branch operation is specified by two macro instructions. The first macro instruction, a compare macro instruction, directs the microproce ...
A translation lookaside buffer (TLB) that caches memory types of memory address ranges. A data unit includes a TLB which, in addition to caching page table entries including translated page base addresses of virtual page numbers as in a conventional TLB, also caches memory address range memory types ...
An apparatus and method for improving the execution of conditional branch instructions is provided. A translator detects a conditional branch instruction during decode of the instruction, and provides a displacement to a target address calculator. The target address calculator calculates a target ad ...
A microprocessor includes re-writeable non-volatile state (RNS) addressable by an instruction executed by the microprocessor that instructs the microprocessor to write a new value to the RNS. A plurality of fuses are each readable to determine whether the fuse is blown or unblown, in response to the ...
A branch predictor for improving branch prediction accuracy is provided. The branch predictor includes global and local Agree dynamic branch predictors, one of which is selected for correlation with a static branch prediction made based upon a test type of a conditional branch instruction specifying ...
An apparatus for speculatively predicting the direction of a branch instruction in a pipelined microprocessor in a hybrid fashion. A branch target address cache (BTAC) stores a direction prediction about executed branch instructions. The BTAC is indexed by an instruction cache fetch address. The BTA ...
An apparatus in an integrated circuit for re-enabling the use of precluded extended JTAG operations. The apparatus includes a JTAG control chain, a feature fuse, a machine specific register, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations ...
A data cache in an in-order single-issue microprocessor that detects cache misses generated by instructions behind a stalled instruction in the microprocessor pipeline and issues memory requests on the processor bus for the missing data so as to overlap with resolution of the stalled instruction, wh ...
