1
Fujio Itomitsu, Yuuichi Saito: Store processing method in a pipelined cache memory. Mitsubishi Denki Kabushiki Kaisha, Townsend and Townsend and Crew, April 16, 1996: US05509137 (38 worldwide citation)

A cache memory apparatus and microprocessor therewith has a first address register for a tag memory and a second address register for a data memory, a tag entry decoder and a data entry decoder. Lower order bits of the contents stored in the first address register are transferred to the second addre ...


2
Fujio Itomitsu, Toyohiko Yoshida: Improved pipelined processor with two stage decoder for exchanging register values for similar operand instructions. Mitsubishi Denki Kabushiki Kaisha, Townsend and Townsend, July 31, 1990: US04945511 (20 worldwide citation)

A pipelined processor to improve the efficiency of conventional pipelined instruction processing including a two stage instruction decoder which converts sets of similar conventional instructions having the general formats: "MOV: A R1 R2" and "MOV: B R1 R2" where the letter fields A,B etc. indicate ...


3
Fujio Itomitsu, Masahito Matsuo: System for selecting control parameter for microinstruction execution unit using parameters and parameter selection signal decoded from instruction. Mitsubishi Denki Kabushiki Kaisha, Townsend and Townsend Khourie and Crew, June 15, 1993: US05220656 (19 worldwide citation)

A device and method for generating execution controlling information (operation designating parameter) for an instruction execution means is provided. The device operates by selecting and composing a parameter (bit field) selected from among the bits of an instruction code and a parameter obtained a ...


4
Fujio Itomitsu, Masahito Matsuo: System for processing parameters in instructions of different format to execute the instructions using same microinstructions. Mitsubishi Denki Kabushiki Kaisha, Townsend and Townsend Khourie and Crew, June 14, 1994: US05321821 (15 worldwide citation)

A device and method for generating execution controlling information (operation designating parameter) for an instruction execution means is provided. The device operates by selecting and composing a parameter (bit field) selected from among the bits of an instruction code and a parameter obtained a ...


5
Fujio Itomitsu, Toyohiko Yoshida: Data processor having branch predicting function. Mitsubishi Denki Kabushiki Kaisha, Lowe Price LeBlanc & Becker, August 8, 1995: US05440704 (12 worldwide citation)

An instruction loaded in an instruction register is decoded by an instruction decoder and the branch predicting bit which indicates whether the instruction is branched or not is read out from a branch predicting mechanism. If it is determined that the instruction is a conditional branch instruction ...


6
Fujio Itomitsu, Kouichi Komawaki: Radio base station device and radio communication method. Mitsubishi Denki Kabushiki Kaisha, Oblon Spivak McClelland Maier & Neustadt P C, September 20, 2005: US06947769 (3 worldwide citation)

A base transceiver station includes a baseband signal processor outputting a frequency notification signal indicating a carrier frequency for modulating a baseband signal, in combination with a baseband signal and a radio transmitter and receiver modulating the baseband signal from the baseband sign ...


7
Kazuhiko Kiyomoto, Kouichi Komawaki, Fujio Itomitsu: Radio base station apparatus. Oblon Spivak Mcclelland Maier & Neustadt PC, October 13, 2005: US20050226311-A1

At the time of modulating transmission data, TRX 35 error-checks the transmission data and outputs the result of the error check, whereas BB 36 error-checks received data output from TRX 35 and makes a health check based on the result of the error check of the received data and the result of error c ...