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Sheng Hsiung Wang, Fu Kai Yang, Yuan Ching Peng, Chi Cheng Hung: Hard mask removal for semiconductor devices. Taiwan Semiconductor Manufacturing Company, Slater & Matsil L, February 12, 2013: US08372719 (3 worldwide citation)

A method of removing a hard mask during fabrication of semiconductor devices is provided. A protective layer, such as a bottom anti-reflective coating (BARC) layer or other dielectric layer, is formed over structures formed on a substrate, wherein spacers are formed alongside the structures. In an e ...


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Audrey Hsiao Chiu Hsu, Fu Kai Yang, Mei Yun Wang, Hsien Cheng Wang, Shih Wen Liu, Hsin Ying Lin: Semiconductor device and method for manufacturing semiconductor device. Taiwan Semiconductor Manufacturing Company, Jones Day, March 29, 2016: US09299657 (2 worldwide citation)

A method for manufacturing semiconductor device is provided. The method includes the following operations: providing a first conductive portion, a second conductive portion and a third conductive portion over a substrate; forming a dielectric layer over the first conductive portion, the second condu ...


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Chen Ming Lee, Liang Yi Chen, Fu Kai Yang, Mei Yun Wang: Semiconductor device and manufacturing method thereof. TAIWAN SEMICONDUCTOR MANUFACTURING, McDermott Will & Emery, June 20, 2017: US09685439 (2 worldwide citation)

A method for manufacturing a semiconductor device is provided, including forming a plurality of fins on a semiconductor substrate, and forming source/drain regions on the fins. The source/drain regions have an uneven surface with a mean surface roughness, Ra, of about 10 nm to about 50 nm. A smoothi ...


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Yenni Yang, Fu Kai Yeh: Photoresist system. Taiwan Semiconductor Manufacturing, Tung & Associates, January 13, 2009: US07477959 (1 worldwide citation)

A photoresist system is disclosed. A graphical user interface of the system allows an operator to initiate a bottle switching operation, among other operations. Barcode data of a photoresist bottle is obtained by an equipment server from a controller. Photoresist data relating to the bottle is obtai ...


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Fu Kai Yang, Shu Huei Suen: Two step trench definition procedure for formation of a dual damascene opening in a stack of insulator layers. Taiwan Semiconductor Manufacturing Company, February 21, 2006: US07001836 (1 worldwide citation)

A process for defining a dual damascene opening in a stack of insulator layers to expose a portion of a top surface of an underlying conductive structure, has been developed. The process features a two step procedure for removal of insulator stop layers, wherein the stop layers are employed to allow ...


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Audrey Hsiao Chiu Hsu, Fu Kai Yang, Mei Yun Wang, Hsien Cheng Wang, Shih Wen Liu, Hsin Ying Lin: Method of forming contact structure of gate structure. Taiwan Semiconductor Manufacturing Company, Jones Day, September 1, 2015: US09123563 (1 worldwide citation)

A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate are etched to expose an underlying silicon substrate. A silicide portion defined by a contact profile is d ...


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Chen Ming Lee, Fu Kai Yang, Hsien Cheng Wang, Mei Yun Wang: Mask-less dual silicide process. Taiwan Semiconductor Manufacturing Company, Slater Matsil, September 6, 2016: US09437495 (1 worldwide citation)

A method of forming a semiconductor device is provided. The method includes forming a mask layer, such as an oxidized layer, over first source/drain regions in a first device region. A dielectric layer, such as an interlayer dielectric layer, is formed and patterned to expose the first source/drain ...


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Chen Ming Lee, Fu Kai Yang, Mei Yun Wang, Kuo Yi Chao: Method for fabricating self-aligned contact in a semiconductor device. TAIWAN SEMICONDUCTOR MANUFACTURING, McDermott Will & Emery, October 9, 2018: US10096525

A semiconductor device includes a gate structure disposed over a substrate, and sidewall spacers disposed on both side walls of the gate structure. The sidewall spacers includes at least four spacer layers including first to fourth spacer layers stacked in this order from the gate structure.