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Ralf Henninger, Franz Hirler, Joachim Krumrey, Walter Rieger, Martin Poelzl: Transistor configuration with a shielding electrode outside an active cell array and a reduced gate-drain capacitance. Infineon Technologies, Laurence A Greenberg, Werner H Stemer, Gregory L Mayback, February 10, 2004: US06690062 (68 worldwide citation)

The switching behavior of a transistor configuration is improved by providing a shielding electrode in an edge region. The shielding electrode surrounds at least sections of an active cell array. The capacitance between an edge gate structure and a drain zone and hence the gate-drain capacitance CGD ...


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Gerald Deboy, Franz Hirler, Martin März, Hans Weber: Switch mode power supply with reduced switching losses. Infineon Technologies, Herbert L Lerner, Laurence A Greenberg, Werner H Stemer, May 14, 2002: US06388287 (67 worldwide citation)

The invention relates to a switching transistor presenting reduced switching losses. In the switching transistor, output capacitance is very high when drain/source voltages are low. As the drain/source voltage increases, the capacitance falls to such low values that the energy stored in the transist ...


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Ralf Henninger, Franz Hirler, Joachim Krumrey, Markus Zundel, Walter Rieger, Martin Pölzl: Semiconductor component with an increased breakdown voltage in the edge area. Infineon Technologies, Laurence A Greenberg, Werner H Stemer, Ralph E Locher, October 19, 2004: US06806533 (66 worldwide citation)

A semiconductor component has a cell array formed in a semiconductor body with a number of identical transistor cells and at least one edge cell formed at an edge of the cell array. Each of the transistor cells has a control electrode, which is formed in a trench, and the edge cell has a field plate ...


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Ralf Henninger, Franz Hirler, Manfred Kotek, Joost Larik, Markus Zundel: Trench power semiconductor. Infineon Technologies, Laurence A Greenberg, Werner H Stemer, Gregory L Mayback, December 21, 2004: US06833584 (66 worldwide citation)

A trench power semiconductor component is described which has an edge cell in which an edge trench is provided. The edge trench, at least on an outer side wall, has a thicker insulating layer than an insulating layer of trenches of the cell array. This simple configuration provides a high dielectric ...


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Ralf Henninger, Franz Hirler, Joachim Krumrey, Walter Rieger, Martin Pölzl, Heimo Hofer: Method for fabricating a transistor configuration including trench transistor cells having a field electrode, trench transistor, and trench configuration. Infineon Technologies, Laurence A Grenberg, Werner H Stemer, Gregory L Mayback, February 28, 2006: US07005351 (62 worldwide citation)

A method for fabricating a transistor configuration including at least one trench transistor cell has a gate electrode and a field electrode disposed in a trench below the gate electrode. The trenches are formed in a semiconductor substrate. A drift zone, a channel zone, and a source zone are in eac ...


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Franz Hirler, Manfred Kotek, Joost Larik, Frank Pfirsch: Trench MOS transistor. Infineon Technologies, Laurence A Greenberg, Werner H Stemer, Gregory L Mayback, April 13, 2004: US06720616 (55 worldwide citation)

A trench MOS-transistor includes a body region strengthened by an implantation area that faces the drain region to increase the avalanche resistance.


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Franz Hirler, Jenoe Tihanyi, Ralf Henninger, Joachim Krumrey, Martin Poelzl, Walter Rieger: Power transistor. Infineon Technologies, Laurence A Greenberg, Werner H Stemer, Ralph E Locher, August 15, 2006: US07091573 (43 worldwide citation)

The power transistor has a trench cell in a semiconductor body. A lower edge of the gate electrode has a profile which is not horizontal, i.e., not planar with respect to the field electrode.


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Joachim Krumrey, Franz Hirler, Ralf Henninger, Martin Pölzl, Walter Rieger: Transistor configuration with a structure for making electrical contact with electrodes of a trench transistor cell. Infineon Technologies, Laurence A Greenberg, Werner H Stemer, Ralph E Locher, May 10, 2005: US06891223 (33 worldwide citation)

Transistor configurations have trench transistor cells disposed along trenches in a semiconductor substrate with two or more electrode structures disposed in the trenches, and also metallizations are disposed above a substrate surface of the semiconductor substrate. The trenches extend into an inact ...


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Wolfgang Werner, Franz Hirler, Joachim Krumrey, Walter Rieger: Semiconductor arrangement with a MOS-transistor and a parallel Schottky-diode. Infineon Technologies, Laurence A Greenberg, Werner H Stemer, Ralph E Locher, February 14, 2006: US06998678 (30 worldwide citation)

The present invention relates to a semiconductor arrangement with a MOS transistor which has a gate electrode (40), arranged in a trench running in the vertical direction of a semiconductor body (100), and a Schottky diode which is connected in parallel with a drain-source path (D-S) and is formed b ...