1
Richard G Cliff, Bahram Ahanin, Craig S Lytle, Francis B Heile, Bruce B Pedersen, Kerry Veenstra: Programmable logic array having local and long distance conductors. Altera Corporation, Robert R Jackson, November 9, 1993: US05260611 (377 worldwide citation)

A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module wit ...


2
Bruce B Pedersen, Richard G Cliff, Bahram Ahanin, Craig S Lytle, Francis B Heile, Kerry S Veenstra: Programmable logic element interconnections for programmable logic array integrated circuits. Altera Corporation, Robert R Jackson, G Victor Treyz, November 9, 1993: US05260610 (349 worldwide citation)

A programmable logic array integrated circuit has a plurality of programmable logic elements grouped into a plurality of mutually exclusive groups. Each group includes signal conductors uniquely associated with that group for conveying signals between the programmable logic elements in that group. O ...


3
Bruce B Pedersen, Richard G Cliff, Bahram Ahanin, Craig S Lytle, Francis B Heile, Kerry S Veenstra: Programmable logic array with local and global conductors. Altera Corporation, G Victor Treyz, Robert R Jackson, Fish & Neave, January 16, 1996: US05485103 (161 worldwide citation)

A programmable logic array integrated circuit has a plurality of programmable logic elements grouped into a plurality of mutually exclusive groups. Each group includes signal conductors uniquely associated with that group for conveying signals between the programmable logic elements in that group. O ...


4
Francis B Heile, Brent A Fairbanks: Work group computing for electronic design automation. Altera Corporation, Beyer & Weaver, November 9, 1999: US05983277 (143 worldwide citation)

A work group computing system for facilitating programmable logic device design among multiple engineers has a global work space including design project source files, a compilation basis, a compilation report text file, a binary assignments database and a user-readable assignments text file. Any nu ...


5
Bruce B Pedersen, David Chiang, Francis B Heile, Cameron McClintock, Hock Chuen So, James A Watson: High-density erasable programmable logic device architecture using multiplexer interconnections. Altera Corporation, Jeffrey H Ingerman, August 31, 1993: US05241224 (135 worldwide citation)

A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to logic array blocks. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes the user's ability to route a selected line t ...


6
Kerry Veenstra, Francis B Heile: Programmable logic architecture incorporating a content addressable embedded array block. Altera Corporation, Beyer Weaver & Thomas, December 4, 2001: US06326807 (114 worldwide citation)

The invention relates to an integrated circuit that can be configured to operate as a content addressable memory. The integrated circuit includes a first functional block that stores at least one keyword dataword which is associated with a group of associated data words. The integrated circuit also ...


7
Richard G Cliff, Francis B Heile, Joseph Huang, David W Mendel, Bruce B Pedersen, Chiakang Sung, Bonnie I Wang: Logic region resources for programmable logic devices. Altera Corporation, Robert R Jackson, Fish & Neave, December 7, 1999: US05999015 (89 worldwide citation)

A programmable logic device has subregions of programmable logic grouped together in logic regions. The subregions in each region share several control signals, which can be selected either from relatively global conductors on the device or from data inputs to the region. The control signals allow s ...


8
Francis B Heile: Programmable logic array device with random access memory configurable as product terms. Altera Corporation, Robert R Jackson, Fish & Neave, February 1, 2000: US06020759 (89 worldwide citation)

A look-up-table-based programmable logic device is provided with memory circuitry which can be operated either as random access memory ("RAM") or to perform product term ("p-term") logic. Each individual row of the memory is separately addressable for writing data to the memory or, in RAM mode, for ...


9
Francis B Heile, Tamlyn V Rawls, Alan L Herrmann, Brent A Fairbanks, David Karchmer: Local compilation in context within a design hierarchy. Altera Corporation, Beyer & Weaver, February 15, 2000: US06026226 (89 worldwide citation)

A technique for allowing local compilation at any level within a design hierarchy tree for a programmable logic device allows a user to compile within the context of the entire design using inherited parameter values and assignments from any parent nodes within the design hierarchy tree. A user is a ...


10
Francis B Heile, Tamlyn V Rawls: Interface for compiling project variations in electronic design environments. Altera Corporation, Beyer Weaver & Thomas, November 20, 2001: US06321369 (85 worldwide citation)

A method is provided in which a base design is generated in the form of one or more data files including assignment data. A variation design is created by adding at least one additional assignment associated with the variation design to the assignment data. The assignment data has an identifier that ...