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Alsup Mitchell, Smaus Gregory William, Pickett James K, Mccinn Brian D, Filippo Michael A, Sander Benjamin T: System and method for handling exceptional instructions in a trace cache based processor. Advanced Micro Devices, Alsup Mitchell, Smaus Gregory William, Pickett James K, Mccinn Brian D, Filippo Michael A, Sander Benjamin T, DRAKE Paul S, May 6, 2005: WO/2005/041024 (4 worldwide citation)

A system may include an instruction cache (106), a trace cache (160) including a plurality of trace cache entries (162), and a trace generator (170) coupled to the instruction cache (106) and the trace cache (160). The trace generator (170) may be configured to receive a group of instructions output ...


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Filippo Michael A, Pickett James K: Processor with dependence mechanism to predict whether a load is dependent on older store. Advanced Micro Devices, Filippo Michael A, Pickett James K, sDRAKE Paul S, March 16, 2006: WO/2006/028555 (4 worldwide citation)

A processor (100) may include a scheduler (118) configured to issue operations and a load store unit (126C) configured to execute memory operations issued by the scheduler. The load store unit (126C) is configured to store information identifying memory operations issued to the load store unit (126C ...


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Alsup Mitchell, Smaus Gregory William, Pickett James K, Mccinn Brian D, Filippo Michael A, Sander Benjamin T: System and method for handling exceptional instructions in a trace cache based processor. Advanced Micro Devices, July 26, 2006: GB2422464-A (3 worldwide citation)

A system may include an instruction cache (106), a trace cache (160) including a plurality of trace cache entries (162), and a trace generator (170) coupled to the instruction cache (106) and the trace cache (160). The trace generator (170) may be configured to receive a group of instructions output ...


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Filippo Michael A, Pickett James K, Sander Benjamin T: System and method for operation replay within a data-speculative microprocessor. Advanced Micro Devices, February 15, 2006: GB2417113-A

A microprocessor (100) may include one or more functional units (126) configured to execute operations, a scheduler (118) configured to issue operations to the functional units (126) for execution, and at least one replay detection unit. The scheduler (118) may be configured to maintain state inform ...


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Filippo Michael A, Pickett James K: Processor with dependence mechanism to predict whether a load is dependent on older store. Advanced Micro Devices, May 30, 2007: GB2432693-A

A processor (100) may include a scheduler (118) configured to issue operations and a load store unit (126C) configured to execute memory operations issued by the scheduler. The load store unit (126C) is configured to store information identifying memory operations issued to the load store unit (126C ...


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Filippo Michael A, Pickett James K, Sander Benjamin T: Speculation pointers to identify data-speculative operations in microprocessor. Advanced Micro Devices, March 15, 2006: GB2418045-A

A microprocessor (100) may include a retire queue (102) and one or more data speculation verification units. The data speculation verification units are each configured to verify data speculation performed on operations. Each data speculation verification unit generates a respective speculation poin ...


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Filippo Michael A, Pickett James K: Store-to-load forwarding buffer using indexed lookup. Advanced Micro Devices, May 17, 2006: GB2420202-A

A microprocessor (100) may include a dispatch unit (104) configured to dispatch load and store operations and a load store unit (126) configured to store information associated with load and store operations dispatched by the dispatch unit (104). The load store unit (126) includes a STLF (Store-to-L ...


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Filippo Michael A, Pickett James K: Processor with dependence mechanism to predict whether a load is dependent on older store. Advanced Micro Devices, chengwei gebo, August 8, 2007: CN200580030152

A processor may include a scheduler configured to issue operations and a load store unit configured to execute memory operations issued by the scheduler. The load store unit is configured to store information identifying memory operations issued to the load store unit. In response to detection of in ...


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Di Filippo Michael A, Di Filippo Teresa M: Capot souple pour conteneur de recyclage, Flexible cover device for a recycle container. Di Filippo Michael A, Di Filippo Teresa M, Di Filippo Michael A, Di Filippo Teresa M, Bereskin & Parr Sencrl, December 22, 2009: CA2413212

A flexible cover device for a recycle container for keeping recyclable articleswithin the container. The flexible cover device for a recycle container includesa net member being made of mesh material; and also includes a first elongatesupport member being securely attached along a first end edge of ...