1
Graham R Wolstenholme, Fernando Gonzalez, Russell C Zahorik: Memory cell incorporating a chalcogenide element and method of making same. Micron Technology, Fletcher Yoder & Van Someren, May 22, 2001: US06236059 (395 worldwide citation)

A memory cell incorporating a chalcogenide element and a method of making same is disclosed. In the method, a doped silicon substrate is provided with two or more polysilicon plugs to form an array of diode memory cells. A layer of silicon nitride is disposed over the plugs. Using a poly-spacer proc ...


2
Graham R Wolstenholme, Steven T Harshfield, Raymond A Turi, Fernando Gonzalez, Guy T Blalock, Donwon Park: Method of making small pores defined by a disposable internal spacer for use in chalcogenide memories. Micron Technology, Fletcher Yoder & Edwards, September 29, 1998: US05814527 (387 worldwide citation)

A method for fabricating an ultra-small pore or contact for use in chalcogenide memory cells specifically and in semiconductor devices generally in which disposable spacers are utilized to fabricate ultra-small pores or contacts. The pores thus defined have minimum lateral dimensions ranging from ap ...


3
Graham R Wolstenholme, Fernando Gonzalez, Russell C Zahorik: Memory cell incorporating a chalcogenide element and method of making same. Micron Technology, Fletcher Yoder & Edwards, December 7, 1999: US05998244 (298 worldwide citation)

A memory cell incorporating a chalcogenide element and a method of making same is disclosed. In the method, a doped silicon substrate is provided with two or more polysilicon plugs to form an array of diode memory cells. A layer of silicon nitride is disposed over the plugs. Using a poly-spacer proc ...


4
Tyler A Lowrey, Randal W Chance, D Mark Durcan, Ruojia Lee, Charles H Dennison, Yauh Ching Liu, Pierre C Fazan, Fernando Gonzalez, Gordon A Haller: Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography. Micron Technology, Angus C Fox III, Stanley N Protigal, May 7, 1991: US05013680 (286 worldwide citation)

A process for creating a DRAM array having feature widths that transcend the resolution limit of the employed photolithographic process using only five photomasking steps. The process involves the following steps: creation of a half-pitch hard-material mask that is used to etch a series of equidista ...


5
Fernando Gonzalez, Raymond A Turi, Graham R Wolstenholme, Charles L Ingalls: Three-dimensional container diode for use with multi-state material in a non-volatile memory cell. Micron Technology, Fletcher Yoder & Edwards, November 3, 1998: US05831276 (254 worldwide citation)

A vertically oriented diode for use in delivering current to a multi-state memory element in a memory cell. A vertical diode may be disposed in a diode container extending downwardly from a top of a silicon or oxide layer, and may be formed of a combination of silicon and/or metal layers disposed pr ...


6
Graham R Wolstenholme, Steven T Harshfield, Raymond A Turi, Fernando Gonzalez, Guy T Blalock, Donwon Park: Small pores defined by a disposable internal spacer for use in chalcogenide memories. Micron Technology, Fletcher Yoder & Van Someren, August 29, 2000: US06111264 (250 worldwide citation)

A method for fabricating an ultra-small pore or contact for use in chalcogenide memory cells specifically and in semiconductor devices generally in which disposable spacers are utilized to fabricate ultra-small pores or contacts. The pores thus defined have minimum lateral dimensions ranging from ap ...


7
Graham R Wolstenholme, Fernando Gonzalez, Russell C Zahorik: Method of making memory cell incorporating a chalcogenide element. Micron Technology, Fletcher Yoder & Van Someren, October 19, 1999: US05970336 (248 worldwide citation)

A memory cell incorporating a chalcogenide element and a method of making same is disclosed. In the method, a doped silicon substrate is provided with two or more polysilicon plugs to form an array of diode memory cells. A layer of silicon nitride is disposed over the plugs. Using a poly-spacer proc ...


8
Fernando Gonzalez, Raymond A Turi: Method for fabricating an array of ultra-small pores for chalcogenide memory cells. Micron Technology, Fletcher & Associates, March 9, 1999: US05879955 (238 worldwide citation)

A method for fabricating an array of ultra-small pores for use in chalcogenide memory cells. A layer of a first material is applied onto a substrate. A portion of the layer of the first material is then removed to define an upper surface with vertical surfaces extending therefrom to a lower surface ...


9
Fernando Gonzalez, Ray Turi: Stack/trench diode for use with a muti-state material in a non-volatile memory cell. Micron Technology, Fletcher Yoder & Edwards, November 24, 1998: US05841150 (236 worldwide citation)

The invention provides a vertically oriented diode for use in delivering large amounts of current to a variable resistance element in a multi-state memory cell. The vertical diode is disposed in a diode container extending downwardly from the top of a tall oxide stack into a deep trench in single cr ...


10
Graham R Wolstenholme, Fernando Gonzalez, Russell C Zahorik: Memory cell incorporating a chalcogenide element. Micron Technology, Fletcher Yoder & Van Someren, November 28, 2000: US06153890 (225 worldwide citation)

A memory cell incorporating a chalcogenide element and a method of making same is disclosed. In the method, a doped silicon substrate is provided with two or more polysilicon plugs to form an array of diode memory cells. A layer of silicon nitride is disposed over the plugs. Using a poly-spacer proc ...