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PIANESE FABIO, EVANS NOAH: [fr] Système de transfert électronique décentralisé, [de] Dezentralisiertes elektronisches Übertragungssystem, [en] Decentralized electronic transfer system. ALCATEL LUCENT, September 4, 2013: EP2634738-A1 (6 worldwide citation)

[en] Method for use in a decentralized electronic transfer system, the method comprising the steps of: - Generating a first digital code representing a first transaction from a first user's secure repository to the first user's unsecure repository - Sending the digital code to a secure storage memor ...


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BOSCH PETER, MULLENDER SAPE, POLAKOS PAUL, EVANS NOAH, HAMPEL GEORG, MCKIE JIM: Method and system for optimising routing between two network nodes, at least one of which is mobile, Verfahren und System zur Optimierung des Routings zwischen zwei Netzwerkknoten, wovon mindestens einer mobil ist, Procédé et système doptimisation de lacheminement entre deux n uds de réseau, dont lun au moins est mobile. ALCATEL LUCENT, March 28, 2012: EP2434707-A1

A method is disclosed for routing packets in an intermediate node between a mobile node and a correspondent node in a packet-switched network, only one of said nodes being macromobility enabled, comprising at the intermediate node: - exchanging lower-layer-address-update-related messages with said m ...


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MULLENDER SAPE, MCKIE JIM BALMER, PIANESE FABIO, EVANS NOAH: A method of managing computer memory, corresponding computer program product, and data storage device therefor, Verfahren zum Verwalten eines Computerspeichers, entsprechendes Computerprogrammprodukt und Datenspeichervorrichtung dafür, Procédé de gestion de la mémoire dun ordinateur, produit de programme informatique correspondant et dispositif de stockage de données correspondant. ALCATEL LUCENT, February 8, 2012: EP2416251-A1

The invention concerns a method of managing computer memory, the method comprising the steps of maintaining (101) a page table entry for mapping a virtual address to a physical address and a cache comprising a plurality of data blocks and, in response to a reference to the virtual address, translati ...


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MULLENDER Sape, MCKIE James Balmer, PIANESE Fabio, EVANS Noah: Procédé de gestion de mémoire informatique, produit-programme dordinateur correspondant ; et dispositif de stockage de données associé, A method of managing computer memory, corresponding computer program product; and data storage device therefor. Alcatel Lucent, MULLENDER Sape, MCKIE James Balmer, PIANESE Fabio, EVANS Noah, MEYER ZU BEXTEN Elmar, February 9, 2012: WO/2012/016783

The invention concerns a method of managing computer memory, the method comprising the steps of maintaining (101) a page table entry for mapping a virtual address to a physical address and a cache comprising a plurality of data blocks and, in response to a reference to the virtual address, translati ...


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BOSCH Peter, MULLENDER Sape, POLAKOS Paul, EVANS Noah, HAMPEL Georg, McKIE Jim: PROCÉDÉ ET SYSTÈME DOPTIMISATION DE ROUTAGE ENTRE DEUX NŒUDS DE RÉSEAU, DONT LUN AU MOINS EST MOBILE, METHOD AND SYSTEM FOR OPTIMISING ROUTING BETWEEN TWO NETWORK NODES, AT LEAST ONE OF WHICH IS MOBILE. ALCATEL LUCENT, BOSCH Peter, MULLENDER Sape, POLAKOS Paul, EVANS Noah, HAMPEL Georg, McKIE Jim, ALU Antw Patent Attorneys, March 29, 2012: WO/2012/038473

A method is disclosed for routing packets in an intermediate node between a mobile node and a correspondent node in a packet-switched network, only one of said nodes being macro- mobility enabled, comprising at the intermediate node: - exchanging lower-layer-address-update-related messages with said ...


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MULLENDER SAPE, MCKIE JAMES, SACHA JAN, SCHILD HENNING, EVANS NOAH: [fr] Système de planification et dexécution de processus de calcul haute performance (HPC) deffort optimal en temps réel, [de] System zur Zeitplanung und Ausführung von Best-Effort-Hochleistungs-Rechenverfahren in Echtzeit, [en] A system for schedule and executing best-effort, real-time and high-performance computing (HPC) processes. ALCATEL LUCENT, September 11, 2013: EP2637096-A1

[en] A system for scheduling and executing best-effort, real-time and high-performance computing (HPC) processes (106, 107), comprising: - a processor with one or more cores (102, 103) - a noise core handling device generated interrupts - a per-core scheduler (141, 151) for best-effort and real-time ...