31

32

33
Eb Eshun
Coolbaugh Douglas D, Eshun Ebenezer E, Hook Terence B, Rassel Robert M, Sprogis Edmund J, Stamper Anthony K, Murphy William J: Heat sink, heat interface and cooling method for resistor. Ibm, zhang gao, September 6, 2006: CN200610005833

A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator i ...


34
Edelstein Daniel C, Chinthakindi Anil K, Dalton Timothy J, Eshun Ebenezer E, Gambino Jeffrey P, Lane Sarah L, Stamper Anthony K: Integrated circuit comb capacitor and forming method thereof. Ibm, yujing liurui dong, July 18, 2007: CN200710001597

The invention is directed to an integrated circuit comb capacitor with capacitor electrodes that have an increased capacitance between neighboring capacitor electrodes as compared with other interconnects and via contacts formed in the same metal wiring level and at the same pitches. The invention a ...


35
Chinthakindi Anil K, Coolbaugh Douglas D, Downes Keith E, Eshun Ebenezer E, Florkey John E, Greer Heidi L, Rassel Robert M, Stamper Anthony K, Vaed Kunal: Semiconductor device and its making method. Ibm, taofeng bei, August 29, 2007: CN200710008138

The present invention provides a semiconductor structure including a buried resistor with improved control, in which the resistor is fabricated in a region of a semiconductor substrate beneath a well region that is also present in the substrate. In accordance with the present invention, the inventiv ...


36
Coolbaugh Douglas D, Eshun Ebenezer E, Gambino Jeffrey P, He Zhong Xiang, Ramachandran Vidhya: Metal-insulator-metal capacitor and method of fabrication. Ibm, June 21, 2006: EP1671358-A2

A method and structure for a MIM capacitor, the structure including: an electronic device, comprising: an interlevel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in the interlevel dielectric layer, a top surface of the bottom electrode co-planer with a top s ...


37
Eshun Ebenezer E, Johnson Jeffrey B, Phelps Richard A, Rassel Robert M, Zierak Michael L: Junction field effect transistor with a hyperabrupt junction. International Business Machines Corporation, Eshun Ebenezer E, Johnson Jeffrey B, Phelps Richard A, Rassel Robert M, Zierak Michael L, KOTULAK Richard M, December 31, 2008: WO/2009/003012

A junction field effect transistor (JFET) (Fig. 4) has a hyperabrupl junction laj cr (54) that functions as a channel of a JFFT. The hyperabrupt junction layer (54) is formed by two dopant profiles (50. 52) of opposite t}pes such that one dopant concentration profile has a peak concentration depth a ...


38
ESHUN EBENEZER E: Metal gate integration structure and method including metal fuse, anti-fuse and/or resistor. INTERNATIONAL BUSINESS MACHINES CORPORATION, Cai Yuanmin, November 19, 2009: WO/2009/140052

A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in ...


39
Eshun Ebenezer E, Johnson Jeffrey B, Phelps Richard A, Rassel Robert M, Zierak Michael L: Junction field effect transistor with a hyperabrupt junction. Ibm, Yu Jing, Yang Xiaoguang, March 24, 2010: CN200880015898

A junction field effect transistor (JFET) has a hyperabrupt junction layer that functions as a channel of a JFET. The hyperabrupt junction layer is formed by two dopant profiles of opposite types suchthat one dopant concentration profile has a peak concentration depth at a tail end of the other dopa ...


40
Coolbaugh Douglas Duane, Eshun Ebenezer E, He Zhong Xiang, Rassel Robert Mark: Mim capacitor and method of making same. Ibm, lichun hui, December 26, 2007: CN200710096585

A MIM capacitor device and method of making the device. The device includes an upper plate comprising one or more electrically conductive layers, the upper plate having a top surface, a bottom surface and sidewalls; a spreader plate comprising one or more electrically conductive layers, the spreader ...