1
Claude Louis Bertin, Wayne John Howell, Erik Leigh Hedberg, Howard Leo Kalter, Gordon Arthur Kelley Jr: Integrated mulitchip memory module, structure and fabrication. International Business Machines Corporation, Heslin & Rothenberg P C, December 30, 1997: US05702984 (124 worldwide citation)

An integrated multichip memory module structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the appearance of a single, higher level memory chip. A memory subunit is form ...


2
Claude Louis Bertin, Erik Leigh Hedberg, James Marc Leas, Steven Howard Voldman: Methods for fabricating multichip semiconductor structures with consolidated circuitry and programmable ESD protection for input/output nodes. International Business Machines Corporation, Heslin & Rothenberg P C, September 15, 1998: US05807791 (81 worldwide citation)

Multichip semiconductor structures with consolidated circuitry are disclosed, along with programmable electrostatic discharge (ESD) protection circuits for chip input/output (I/O) nodes. The multichip structures include a first semiconductor chip having a first circuit at least partially providing a ...


3
Claude Louis Bertin, John A Fifield, Erik Leigh Hedberg, Russell J Houghton, Timothy Dooling Sullivan, Steven William Tomashot, William Robert Tonti: Impedance control using fuses. International Business Machines Corporation, Howard J Walker Jr esq, Scully Scott Murphy & Presser, October 31, 2000: US06141245 (65 worldwide citation)

A system and method for reducing impedance loading of semiconductor integrated circuit devices implementing protective device structures that contributes to impedance loading at an I/O pad connection. The method comprises providing a fuse device between the I/O pad connection and the protective devi ...


4
Claude Louis Bertin, Erik Leigh Hedberg, Wayne John Howell: Semiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit. Internatinal Business Machines Corporation, Heslin & Rothernberg P C, August 31, 1999: US05946545 (58 worldwide citation)

Electronic semiconductor structures, and fabrication and sparing methods, each utilize an electrically programmable spare circuit incorporated with a multichip package. The programmable sparing capability in the multichip package is accomplished either with or without the inclusion of a spare chip(s ...


5
Erik Leigh Hedberg, Garrett Stephen Koch: Method and apparatus for real time two dimensional redundancy allocation. International Business Machines Corporation, Robert A Walsh, January 12, 1999: US05859804 (50 worldwide citation)

A method and apparatus are provided in an array built in self test (ABIST) environment formed on a semiconductor chip having an array of memory cells arranged in columns and rows and column and row redundant lines which includes testing the array along the columns to identify a given number of fault ...


6
David Elson Douse, Wayne Frederick Ellis, Erik Leigh Hedberg: Memory device with programmable self-refreshing and testing methods therefore. International Business Machines Corporation, Heslin & Rothenberg, December 30, 1997: US05703823 (46 worldwide citation)

A programmable self-time refresh circuit for a semiconductor memory and methods for programming the self-refresh rate for non-invasively and deterministically testing the self-timed refresh circuit for establishing/verifying a refresh rate and a wait state interval for the self-refresh operation. Th ...


7
Claude Louis Bertin, John Joseph Ellis Monaghan, Erik Leigh Hedberg, Terence Blackwell Hook, Jack Allan Mandelman, Edward Joseph Nowak, Wilbur David Pricer, Minh Ho Tong, William Robert Tonti: Switched body SOI (silicon on insulator) circuits and fabrication method therefor. International Business Machines Corporation, John J Goodwin, May 29, 2001: US06239649 (33 worldwide citation)

Circuits with SOI devices are coupled to a body bias voltage via a switch for selectively connecting the body bias voltage signals to the SOI device body. NMOS or PMOS SOI devices are used for the switched body SOI device and a FET is used for the switch and the gate terminal of the SOI device is co ...


8
Claude Louis Bertin, Erik Leigh Hedberg, Timothy Dooling Sullivan, William Robert Tonti: Chip thermal protection device. International Business Machines Corporation, Howard J Walter Jr, Scully Scott Murphy & Presser, April 17, 2001: US06219215 (25 worldwide citation)

A gap conducting structure for an integrated electronic circuit that functions as an electronic fuse device and that is integrated as part of the semi-conductor chip wiring for providing over-current and thermal runaway protection. The gap conducting structure includes one or more air gap regions of ...


9
Erik Leigh Hedberg, Garrett Stephen Koch: Method and apparatus for real time two dimensional redundancy allocation. International Business Machines Corporation, Robert A Walsh, February 15, 2000: US06026505 (24 worldwide citation)

A method and apparatus are provided in an array built in self test (ABIST) environment formed on a semiconductor chip having an array of memory cells arranged in columns and rows and column and row redundant lines which includes testing the array along the columns to identify a given number of fault ...


10
Claude Louis Bertin, John A Fifield, Erik Leigh Hedberg, Russell J Houghton, Timothy Dooling Sullivan, Steven William Tomashot, William Robert Tonti: Impedance control using fuses. International Business Machines Corporation, Howard J Walter Jr Esq, Scully Scott Murphy & Presser, June 5, 2001: US06243283 (16 worldwide citation)

A system and method for reducing impedance loading of semiconductor integrated circuit devices implementing protective device structures that contributes to impedance loading at an I/O pad connection. The method comprises providing a fuse device between the I/O pad connection and the protective devi ...