1
James A Bauman, Eric T Anderson: Method and apparatus for supplying requests to a scheduler in an input buffered multiport switch. Cabletron Systems, Mark A Wilson, Law Offices of Mark A Wilson, December 12, 2000: US06160812 (104 worldwide citation)

A method and apparatus for supplying new requests to a scheduler in an input-buffered multiport switch involve selecting a request that does not target output channels that conflict with output channels targeted by requests that are already accessible to the scheduler. Specifically, target output ch ...


2
J Arjun Prabhu, Philip A Ferolito, Eric T Anderson, James A Bauman: Auxiliary register file accessing technique. Sun Microsystems, The Gunnison Law Firm, December 1, 1998: US05845307 (16 worldwide citation)

Certain bits in existing op code formats for a processor do not change from one instruction to another when particular classes of instructions are used. Applicants optionally utilize one or more of these bits to identify one of a plurality of different register files from which to retrieve operands ...


3
Brian Fahs, Eric T Anderson, Nick Barrow Williams, Shirish Gadre, Joel James McCormack, Bryon S Nordquist, Nirmal Raj Saxena, Lacky V Shah: Technique for performing memory access operations via texture hardware. NVIDIA Corporation, Artegis Law Group, July 4, 2017: US09697006

A texture processing pipeline can be configured to service memory access requests that represent texture data access operations or generic data access operations. When the texture processing pipeline receives a memory access request that represents a texture data access operation, the texture proces ...


4
Brian Fahs, Eric T Anderson, Nick Barrow Williams, Shirish Gadre, Joel James McCormack, Bryon S Nordquist, Nirmal Raj Saxena, Lacky V Shah: Technique for performing memory access operations via texture hardware. NVIDIA CORPORATION, Artegis Law Group, August 1, 2017: US09720858

A texture processing pipeline can be configured to service memory access requests that represent texture data access operations or generic data access operations. When the texture processing pipeline receives a memory access request that represents a texture data access operation, the texture proces ...


5
Brian Fahs, Eric T Anderson, Nick Barrow Williams, Shirish Gadre, Joel James McCormack, Bryon S Nordquist, Nirmal Raj Saxena, Lacky V Shah: Technique for accessing content-addressable memory. NVIDIA Corporation, Artegis Law Group, May 24, 2016: US09348762

A tag unit configured to manage a cache unit includes a coalescer that implements a set hashing function. The set hashing function maps a virtual address to a particular content-addressable memory unit (CAM). The coalescer implements the set hashing function by splitting the virtual address into upp ...


6
Philip Payman Shirvani, Peter Sommers, Eric T Anderson: Approach to reducing voltage noise in a stalled data pipeline. NVIDIA CORPORATION, Artegis Law Group, August 7, 2018: US10043230

Computer and graphics processing elements, connected generally in series, form a pipeline. Circuit elements known as di/dt throttles are inserted within the pipeline at strategic locations where the potential exists for data flow to transition from an idle state to a maximum data processing rate. Th ...


7
Steven J Heinrich, Eric T Anderson, Jeffrey A Bolz, Jonathan Dunaisky, Ramesh Jandhyala, Joel McCormack, Alexander L Minkin, Bryon S Nordquist, Poornachandra Rao: Load/store operations in texture hardware. NVIDIA Corporation, Artegis Law Group, March 14, 2017: US09595075

Approaches are disclosed for performing memory access operations in a texture processing pipeline having a first portion configured to process texture memory access operations and a second portion configured to process non-texture memory access operations. A texture unit receives a memory access req ...


8
Eric T Anderson, Poornachandra Rao: Approach to caching decoded texture data with variable dimensions. NVIDIA CORPORATION, Artegis Law Group, July 24, 2018: US10032246

A texture processing pipeline is configured to store decoded texture data within a cache unit in order to expedite the processing of texture requests. When a texture request is processed, the texture processing pipeline queries the cache unit to determine whether the requested data is resident in th ...


9
Philip Payman Shirvani, Peter Benjamin Sommers, Eric T Anderson: Voltage droop reduction by delayed back-propagation of pipeline ready signal. NVIDIA Corporation, Zilka Kotab PC, March 22, 2016: US09292295

A system, method, and computer program product for generating flow-control signals for a processing pipeline is disclosed. The method includes the steps of generating, by a first pipeline stage, a delayed ready signal based on a downstream ready signal received from a second pipeline stage and a thr ...


10
Eric T Anderson, Peter Pittman: Schefflera Fan. David B Waller & Associates, April 6, 2006: US20060075536-P1

A distinct cultivar of Schefflera plant named ‘Fan’, characterized by its upright plant habit: rapid growth rate; closely-spaced leaves and parted palmate leaves that are palmately veined, very glossy and dark green which give a dense full appearance.