1
Jeffrey Scott Salowe, Steven Lee Pucci, Eric Nequist: Nearest neighbor mechanism. Cadence Design Systems, Bingham McCutchen, December 27, 2005: US06981235 (19 worldwide citation)

A method of analyzing a design of an electronic circuit may include selecting a query object in a collection of sets of intervals for the design, where each set of intervals along a first common axis, the collection of sets along a second common axis. Candidate objects within the collection that are ...


2
Eric Nequist, Jeffrey Scott Salowe, Steven Lee Pucci: Zone tree method and mechanism. Cadence Design Systems, Bingham McCutchen, August 29, 2006: US07100128 (18 worldwide citation)

A method of analyzing a design of an electronic circuit uses slices. The method includes generating one or more slices, each slice comprising a contiguous region of the design, and generating an set comprising one or more bins for each slice. A search for an object may be performed by determining a ...


3
David White, Roland Ruehl, Eric Nequist: System and method for layout optimization using model-based verification. Cadence Design Systems, Vista IP Law Group, May 25, 2010: US07725845 (13 worldwide citation)

Method and system for chip optimization using model based verification (MBV) tool provide more accurate verification in determining hotspots and their characteristics. The MBV and the layout optimizer are implemented within a feedback loop. This type of verification allows for the MBV tool to provid ...


4
Eric Nequist: Shape abstraction mechanism. Cadence Design Systems, Bingham McCutchen, January 3, 2006: US06983440 (13 worldwide citation)

A method of simulating a design of an electronic system having multiple layers includes, for each layer, storing a plurality of shape occurrences for the layer. A hierarchy of shape instances having a plurality of levels is generated. Each shape instance corresponds to one of the shape occurrences. ...


5
Eric Nequist: Method and mechanism for determining shape connectivity. Cadence Design Systems, Vista IP Law Group, December 2, 2008: US07461359 (10 worldwide citation)

A method and mechanism is disclosed for identifying connected shapes and objects in an electrical design. The entire hierarchical design does not have to be flattened to perform the operation of identifying connected objects for a specific object. Instead of unfolding the entire design hierarchy, on ...


6
Richard Brashears, Eric Nequist: Method and system for implementing routing refinement and timing convergence. Cadence Design Systems, Vista IP Law Group, February 2, 2010: US07657860 (8 worldwide citation)

Disclosed is an improved method, system, and article of manufacture for implementing routing for an electrical circuit and chip design. A routing architecture can be represented as a spectrum of different granular routing levels. Instead of routing based upon area, routing can be performed for speci ...


7
Eric Nequist, Richard Brashears: Representation, configuration, and reconfiguration of routing method and system. Cadence Design Systems, Vista IP Law Group, November 3, 2009: US07614028 (7 worldwide citation)

Disclosed is an improved method, system, and article of manufacture for implementing routing for an electrical circuit and chip design. A routing architecture can be represented as a spectrum of different granular routing levels. Instead of routing based upon area, routing can be performed for speci ...


8
Jeffrey Scott Salowe, Eric Nequist: Hierarchical gcell method and mechanism. Cadence Design Systems, Bingham McCutchen, August 29, 2006: US07100129 (6 worldwide citation)

A method of analyzing a design of an electronic circuit includes tessellating the design into a grid of rectangles, selecting at least one rectangle as a first level parent rectangle, and generating a plurality of second level child rectangles based on the first level parent rectangle.


9
Eric Nequist: Method and mechanism for identifying and tracking shape connectivity. Cadence Design Systems, Vista IP Law Group, February 16, 2010: US07665045 (6 worldwide citation)

A method and mechanism is disclosed for identifying and tracking nets in an electrical design. A hierarchical design does not have to be flattened to perform the operation of identifying and tracking nets. To identify sets of connected shapes, instead of having to unfold the entire design hierarchy, ...


10
David White, Eric Nequist: Method and system for model-based routing of an integrated circuit. Cadence Design Systems, Vista IP Law Group, December 28, 2010: US07861203 (5 worldwide citation)

Disclosed is a method, system, and computer program product for implementing model-based floorplanning, layout, placement, and routing. Models are used to guide the placement and routing of polygons on the IC layout based upon predictions of manufacturing variations.